ICS841S02BGILF IDT, Integrated Device Technology Inc, ICS841S02BGILF Datasheet - Page 3

IC CLK GENERATOR PLL 20-TSSOP

ICS841S02BGILF

Manufacturer Part Number
ICS841S02BGILF
Description
IC CLK GENERATOR PLL 20-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Distribution, Spread Spectrum Clock Generatorr
Datasheet

Specifications of ICS841S02BGILF

Input
Crystal
Output
HCSL
Frequency - Max
100MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Frequency-max
100MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1129
800-1129-5
800-1129
841S02BGILF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS841S02BGILF
Manufacturer:
AVAGO
Quantity:
3 861
S
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting upon power-up, and therefore, use of this
interface is optional. Clock device register changes are nor-
mally made upon system initialization, if any are required. The
interface cannot be used during system operation for power
management functions.
IDT
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2
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ERIAL
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ICS841S02I
PCI EXPRESS™ CLOCK GENERATOR
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The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in Table 3A.
The block write and block read protocol is outlined in Table 3B,
while Table 3C outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
a
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ICS841S02BGI REV. C NOVEMBER 1, 2007
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PRELIMINARY

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