FS6377-01IG-XTD ON Semiconductor, FS6377-01IG-XTD Datasheet - Page 11

IC CLOCK GEN 3-PLL PROGR 16-SOIC

FS6377-01IG-XTD

Manufacturer Part Number
FS6377-01IG-XTD
Description
IC CLOCK GEN 3-PLL PROGR 16-SOIC
Manufacturer
ON Semiconductor
Type
PLL Clock Generatorr
Datasheet

Specifications of FS6377-01IG-XTD

Pll
Yes
Input
Crystal
Output
CMOS
Number Of Circuits
1
Ratio - Input:output
1:4
Differential - Input:output
No/No
Frequency - Max
230MHz
Divider/multiplier
Yes/No
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Frequency-max
230MHz
Number Of Elements
3
Pll Input Freq (min)
5MHz
Pll Input Freq (max)
27MHz
Operating Supply Voltage (typ)
3.3/5V
Operating Temp Range
-40C to 85C
Package Type
SOIC
Output Frequency Range
0.8 to 150MHz
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Pin Count
16
Mounting Style
SMD/SMT
Number Of Outputs
1
Operating Temperature Range
0 C to + 70 C
Supply Current
43 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
766-1027

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FS6377-01IG-XTD
Manufacturer:
ON Semiconductor
Quantity:
135
Part Number:
FS6377-01IG-XTD
Manufacturer:
Exar
Quantity:
40
FS6377
6.2 Power-Down
All power-down functions are controlled by enable bits. The bits select which portions of the device to power-down when the PD input is
asserted.
Table 4: Power-Down Bits
Table 5: Divider Control Bits
Name
PDPLL_A
(Bit 21)
PDLL_B
(Bit 45)
PDLL_C
(Bit 69)
Reserved (0)
(Bit 69)
PDPOSTA
(Bit 120)
PDPOSTB
(Bit 121)
PDPOSTC
(Bit 122)
PDPOSTD
(Bit 123)
Name
REFDIV_A[7:0]
(Bits 7-0)
REFDIV_B[7:0]
(Bits 31-24)
REFDIV_C1[7:0]
(Bits 55-48)
REFDIV_C2[7:0]
(Bits 79-72)
FBKDIV_A[10:0]
(Bits 18-8)
FBKDIV_B[10:0]
(Bits 42-32)
FBKDIV_C1[10:0]
(Bits 66-56)
FBKDIV_C2[10:0]
(Bits 90-80)
Description
Power-Down PLL A
Bit = 0
Bit = 1
Power-Down PLL B
Bit = 0
Bit = 1
Power-Down PLL C
Bit = 0
Bit = 1
Set these reserved bits to zero (0)
Power-Down POST Divider A
Bit = 0
Bit = 1
Power-Down POST Divider B
Bit = 0
Bit = 1
Power-Down POST Divider C
Bit = 0
Bit = 1
Power-Down POST Divider D
Bit = 0
Bit = 1
Description
Reference Divider A (N
Reference Divider B (N
Reference Divider C1 (N
selected when the SEL_CD pin = 0
Reference Divider C2 (N
selected when the SEL_CD pin = 1
Feedback Divider A (N
FBKDIV_A[2:0]
FBKDIV_A[10:3]
Feedback Divider B (N
FBKDIV_B[2:0]
FBKDIV_B[10:3]
Feedback Divider C1 (N
selected when the SEL_CD pin = 0
FBKDIV_C1[2:0]
FBKDIV_C1[10:3]
Feedback Divider C2 (N
selected when the SEL_CD pin = 1
FBKDIV_C2[2:0]
FBKDIV_C2[10:3]
Power on
Power off
Power on
Power off
Power on
Power off
Power on
Power off
Power on
Power off
Power on
Power off
Power on
Power off
A-Counter value
M-Counter value
A-Counter value
M-Counter value
A-Counter value
M-Counter value
A-Counter value
M-Counter value
R
R
F
F
)
)
R
R
)
)
F
F
)
)
)
)
Rev. 4 | Page 11 of 24 | www.onsemi.com

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