ICS874003AGLF IDT, Integrated Device Technology Inc, ICS874003AGLF Datasheet

ICS874003AGLF

Manufacturer Part Number

ICS874003AGLF

Description

IC JITTER ATTENUATOR 20-TSSOP

Manufacturer

IDT, Integrated Device Technology Inc

Series

HiPerClockS™r

Type

Jitter Attenuatorr

Datasheet

1.ICS874003AGLF.pdf (14 pages)

Specifications of ICS874003AGLF

Input

HCSL, LVDS, LVHSTL, LVPECL, SSTL

Output

LVDS

Frequency - Max

160MHz

Voltage - Supply

3.135 V ~ 3.465 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

20-TSSOP

Frequency-max

160MHz

Number Of Elements

Supply Current

75mA

Pll Input Freq (min)

98MHz

Pll Input Freq (max)

128MHz

Operating Supply Voltage (typ)

3.3V

Operating Temp Range

0C to 70C

Package Type

TSSOP

Output Frequency Range

98 to 160MHz

Operating Supply Voltage (min)

3.135V

Operating Supply Voltage (max)

3.465V

Operating Temperature Classification

Commercial

Pin Count

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

800-1215
800-1215-5
800-1215
874003AGLF

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

ICS874003AGLF

Manufacturer:

IDT Integrated Device Technolo

Quantity:

135

Current page: 1 of 14
Download datasheet (175Kb)

The ICS874003 is a high performance Differential-to-LVDS

Jitter Attenuator designed for use in PCI Express systems.

In some PCI Express systems, such as those found in

desktop PCs, the PCI Express clocks are generated from a

low bandwidth, high phase noise PLL frequency

synthesizer. In these systems, a jitter attenuator may be

required to attenuate high frequency random and

deterministic jitter components from the PLL synthesizer

and from the system board. The ICS874003 has 3 PLL

bandwidth modes: 200kHz, 400kHz, and 800kHz. The

200kHz mode will provide maximum jitter attenuation, but

with higher PLL tracking skew and spread spectrum

modulation from the motherboard synthesizer may be

attenuated. The 400kHz provides an intermediate bandwidth

that can easily track triangular spread profiles, while

providing good jitter attenuation. The 800kHz bandwidth

provides the best tracking skew and will pass most spread

profiles, but the jitter attenuation will not be as good as the

lower bandwidth modes. Because some 2.5Gb serdes have

x20 multipliers while others have than x25 multipliers, the

ICS874003 can be set for 1:1 mode or 5/4 multiplication

mode (i.e. 100MHz input/125MHz output) using the FSEL pins.

The ICS874003 uses IDT’s 3

PLL technology to achive the lowest possible phase noise.

The device is packaged in a 20 Lead TSSOP package,

making it ideal for use in space constrained applications

such as PCI Express add-in cards.

BW_SEL

874003AG

F_SELB

F_SELA

nCLK

ENERAL

LOCK

OEA

OEB

CLK

Pullup

Pulldown

Float

Float = ~400kHz

Pulldown

Pullup

Pulldown

0 = ~200kHz

1 = ~800kHz

IAGRAM

ESCRIPTION

Detector

Phase

M = ÷5

Generation FemtoClock

(fixed)

490 - 640MHz

VCO

www.idt.com

F_SELB

F_SELA

PLL B

÷5

÷4

÷5

÷4

BW_SEL

0 = PLL Bandwidth: ~200kHz

Float = PLL Bandwidth: ~400kHz (default)

1 = PLL Bandwidth: ~800kHz

Three Differential LVDS output pairs

One Differential clock input

CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

Output frequency range: 98MHz - 160MHz

Input frequency range: 98MHz - 128MHz

VCO range: 490MHz - 640MHz

Cycle-to-cycle jitter: 35ps (maximum)

3.3V operating supply

Three bandwidth modes allow the system designer to

make jitter attenuation/tracking skew design trade-offs

0°C to 70°C ambient operating temperature

Available in both standard and lead-free RoHS compliant

packages

EATURES

(default)

ANDWIDTH

QA0

nQA0

QA1

nQA1

QB0

nQB0

BW_SEL

F_SELA

ITTER

6.5mm x 4.4mm x 0.92mm

ICS874003

nQA0

QA1

QA0

DDO

DDA

20-Lead TSSOP

ICS874003

PCI E

G Package

package body

SSIGNMENT

REV. A OCTOBER 5, 2010

Top View

TTENUATOR

XPRESS

nQA1

QB0

nQB0

F_SELB

OEB

GND

nCLK

CLK

OEA

DDO

Related parts for ICS874003AGLF

ICS874003AGLF Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS874003 is a high performance Differential-to-LVDS Jitter Attenuator designed for use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG T 4A ABLE ...

Page 4

T 4C ABLE IFFERENTIAL HARACTERISTICS ...

Page 5

P ARAMETER V DD DDO DDA 3.3V±5% POWER SUPPLY LVDS Float GND + – 3.3V LVDS UTPUT OAD EST nQA0:nQA1, nQB0 QA0:QA1, QB0 ➤ ➤ ➤ t cycle jit(cc) = ...

Page 6

OWER UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS874003 provides sepa- rate power supplies to isolate any high switching noise from the outputs ...

Page 7

IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING the V and V input requirements. Figures show PP CMR interface examples for ...

Page 8

LVDS D T RIVER ERMINATION A general LVDS inteface is shown in Figure 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 3.3V LVDS_Driv er 100 Ohm Differiential Transmission Line 874003AG receiver ...

Page 9

This section provides information on power dissipation and junction temperature for the ICS874003. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS874003 is the sum of the core power plus the power ...

Page 10

ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second ...

Page 11

ACKAGE UTLINE UFFIX FOR T ABLE Reference Document: JEDEC Publication 95, MO-153 874003AG TSSOP EAD ACKAGE IMENSIONS ...

Page 12

ABLE RDERING NFORMATION ...

Page 13

...

Page 14

We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...

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