ICS97U877AHLF IDT, Integrated Device Technology Inc, ICS97U877AHLF Datasheet
ICS97U877AHLF
Specifications of ICS97U877AHLF
97U877AHLF
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ICS97U877AHLF Summary of contents
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Integrated Circuit Systems, Inc. 1.8V Wide Range Frequency Clock Driver Recommended Application: • DDR2 Memory Modules / Zero Delay Board Fan Out • Provides complete DDR DIMM logic solution with ICSSSTU32864 Product Description/Features: • Low skew, low jitter PLL clock ...
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ICS97U877 Pin Descriptions ...
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Function Table ...
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ICS97U877 Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD -0.5V to 2.5V Logic Inputs . . . . . . . . . . . . . . . . . ...
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Recommended Operating Condition (see note1 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A SYMBOL PARAMETER V Supply Voltage DDQ V Low level input voltage V High level input voltage DC ...
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ICS97U877 Timing Requirements 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization Switching Characteristics ...
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VDD/2 ICS97U877 -VDD FB_OUTC FB_OUTT X 0792A—04/15/04 Parameter Measurement Information V DD ICS97U877 GND Figure 1. IBIS Model Output Load GND ...
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ICS97U877 CLK_INC CLK_INT FB_INC FB_INT FB_OUTC FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 0792A—04/15/04 Parameter Measurement Information t ( ...
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Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 0792A—04/15/04 Parameter Measurement Information t jit(hper_n) t jit(hper_n+ jit(hper) jit(hper_n) 2xf O Figure 7. Half-Period Jitter 80% t slr ...
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ICS97U877 CK CK FBIN FBIN t ( )dyn Figure 10. Time delay between OE and Clock Output (Y, Y) 0792A—04/15/ SSC OFF SSC )dyn Figure 9. Dynamic Phase ...
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Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one GND via (farthest from PLL). - Recommended ...
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ICS97U877 A1 D TOP VIEW E ALL DIMENSIONS IN MILLIMETERS Min/Max 7.00 Bsc 4.50 Bsc 0.86/1.00 0.65 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: ...
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Index Area Top View D THERMALLY ENHANCED, VERY THIN, FINE PITCH BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. Source Reference: MLF2™ SER ...