CY2291FX Cypress Semiconductor Corp, CY2291FX Datasheet - Page 9

• Manufacturer Part Number: CY2291FX
• Description: IC 3PLL EPROM CLOCK GEN 20-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY2291FX

• Number Of Circuits: 1
• Package / Case: 20-SOIC (7.5mm Width)
• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 66.6MHz, 90MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 66.6MHz/90MHz
• Maximum Input Frequency: 30 MHz
• Minimum Input Frequency: 1 MHz
• Output Frequency Range: 0.076923 MHz to 90 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• Clock Ic Type: PLL Clock Generator
• Frequency: 90MHz
• No. Of Outputs: 8
• Supply Current: 75mA
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Digital Ic Case Style: SOIC
• No. Of Pins: 18
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3093 - SOCKET ADAPTER FTG FOR CY2291F428-1457 - KIT DEV FTG PROGRAMMING KIT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2184-5; CY2291FX

Switching Characteristics, Commercial 3.3 V
Document Number: 38-07189 Rev. *E
t
t
t
t
t
t
Note
Parameter
9A
9B
9C
9D
10A
10B
27. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application
note: “Jitter in PLL-Based Systems.
Clock jitter
Clock jitter
Clock jitter
Clock jitter
Lock time for
CPLL
Lock time for
UPLL and SPLL
Slew limits
Name
[27]
[27]
[27]
[27]
Peak-to-peak period jitter (t
clock period (f
Peak-to-peak period jitter (t
< f
Peak-to-peak period jitter
(16 MHz < f
Peak-to-peak period jitter
(f
Lock time from power-up
Lock time from power-up
CPU PLL slew limits
OUT
OUT
> 50 MHz)
< 16 MHz)
OUT
OUT
< 50 MHz)
< 4 MHz)
Description
9A
9B
CY2291
CY2291F
Max. – t
Max. – t
9A
9B
min.),% of
min.) (4 MHz
Min






8
8
< 0.25
< 400
< 250
< 0.5
< 0.7
< 25
Typ


Max
66.6
500
350
50
80
1
1
1
CY2291
Page 9 of 17
MHz
MHz
Unit
ms
ms
ns
ps
ps
%
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