CY2291FX Cypress Semiconductor Corp, CY2291FX Datasheet - Page 11

• Manufacturer Part Number: CY2291FX
• Description: IC 3PLL EPROM CLOCK GEN 20-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generator, Fanout Distributionr

Specifications of CY2291FX

• Number Of Circuits: 1
• Package / Case: 20-SOIC (7.5mm Width)
• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 66.6MHz, 90MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 66.6MHz/90MHz
• Maximum Input Frequency: 30 MHz
• Minimum Input Frequency: 1 MHz
• Output Frequency Range: 0.076923 MHz to 90 MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• Clock Ic Type: PLL Clock Generator
• Frequency: 90MHz
• No. Of Outputs: 8
• Supply Current: 75mA
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Digital Ic Case Style: SOIC
• No. Of Pins: 18
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3093 - SOCKET ADAPTER FTG FOR CY2291F428-1457 - KIT DEV FTG PROGRAMMING KIT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2184-5; CY2291FX

Switching Characteristics, Industrial 3.3 V
Document Number: 38-07189 Rev. *E
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes
Parameter
1
3
4
5
6
7
8
9A
9B
9C
9D
10A
10B
34. XBUF duty cycle depends on XTALIN duty cycle
35. Measured at 1.4 V.
36. Measured between 0.4 V and 2.4 V.
37. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information
38. CLKF is not guaranteed to be in phase with CLKA-D, even if it is referenced off the same PLL
39. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application
note: “Jitter in PLL-Based Systems.
Output period
Output duty
cycle
Rise time
Fall time
Output disable
time
Output enable
time
Skew
CPUCLK slew
Clock jitter
Clock jitter
Clock jitter
Clock jitter
Lock time for
CPLL
Lock time for
UPLL and SPLL
Slew limits
Name
[34]
[39]
[39]
[39]
[39]
Clock output range, 3.3 V
operation
Duty cycle for outputs, defined as t
f
Duty cycle for outputs, defined as t
f
Output clock rise time
Output clock fall time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related outputs
35, 38]
Frequency transition rate
Peak-to-peak period jitter (t
clock period (f
Peak-to-peak period jitter (t
< f
Peak-to-peak period jitter
(16 MHz < f
Peak-to-peak period jitter (f
Lock time from power-up
Lock time from power-up
CPU PLL slew limits
OUT
OUT
OUT
> 66 MHZ
< 66 MHZ
< 16 MHz)
OUT
OUT
< 50 MHz)
< 4 MHz)
[36]
Description
[36]
9A
9B
OUT
CY2291I
CY2291FI
CY2291I
CY2291FI
Max. – t
Max. – t
> 50 MHz)
2
2
 t
 t
9A
9B
1
1
[35]
[35]
min.),% of
min.) (4 MHz
[37,
(66.6 MHz)
(60 MHz)
16.66
40%
45%
Min
1.0
15
8
8











< 0.25
< 0.25
< 400
< 250
< 0.5
< 0.7
50%
50%
< 25
Typ
2.5
10
10
3




(76.923 kHz)
(76.923 kHz)
13000
13000
60%
55%
Max
20.0
66.6
500
350
0.5
15
15
50
60
5
4
1
1
1
Page 11 of 17
CY2291
MHz/ms
MHz
MHz
Unit
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
%


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