CY2291FX Cypress Semiconductor Corp, CY2291FX Datasheet - Page 7

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CY2291FX

Manufacturer Part Number
CY2291FX
Description
IC 3PLL EPROM CLOCK GEN 20-SOIC
Manufacturer
Cypress Semiconductor Corp
Type
Clock Generator, Fanout Distributionr
Datasheets

Specifications of CY2291FX

Number Of Circuits
1
Package / Case
20-SOIC (7.5mm Width)
Pll
Yes
Input
Clock, Crystal
Output
Clock, Crystal
Ratio - Input:output
1:8
Differential - Input:output
No/No
Frequency - Max
66.6MHz, 90MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.3V, 5V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
66.6MHz/90MHz
Maximum Input Frequency
30 MHz
Minimum Input Frequency
1 MHz
Output Frequency Range
0.076923 MHz to 90 MHz
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V, 5 V
Clock Ic Type
PLL Clock Generator
Frequency
90MHz
No. Of Outputs
8
Supply Current
75mA
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Digital Ic Case Style
SOIC
No. Of Pins
18
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY3093 - SOCKET ADAPTER FTG FOR CY2291F428-1457 - KIT DEV FTG PROGRAMMING KIT
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2184-5
CY2291FX

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY2291FX
Manufacturer:
VISHAY
Quantity:
4 932
Electrical Characteristics, Industrial 3.3 V
Switching Characteristics, Commercial 5.0 V
Document Number: 38-07189 Rev. *E
V
V
V
V
V
V
I
I
I
I
I
I
t
t
t
t
t
t
t
Notes
Parameter
Parameter
IH
IL
OZ
DD
DDS
BATT
1
3
4
5
6
7
8
13. Xtal inputs have CMOS thresholds.
14. Load = Max., V
15. XBUF duty cycle depends on XTALIN duty cycle.
16. Measured at 1.4 V.
17. Measured between 0.4V and 2.4 V.
18. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information.
19. Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to the application
20. CLKF is not guaranteed to be in phase with CLKA-D, even if it is referenced off the same PLL
OH
OL
OH–32
OL–32
IH
IL
(multiply by 0.65 for 3V operation): I
note: “Jitter in PLL-Based Systems.”
Output period
Output duty
cycle
Rise time
Fall time
Output disable
time
Output enable
time
Skew
CPUCLK Slew
HIGH-level output voltage
LOW-level output voltage
32.768-kHz HIGH-level
output voltage
32.768-kHz LOW-Level
Output Voltage
HIGH-level input voltage
LOW-level input voltage
Input HIGH current
Input LOW current
Output leakage current
V
industrial
V
shutdown mode
V
DD
DD
BATT
IN
Name
= 0 V or V
[15]
power supply current in
supply current
power supply current V
Description
DD
, Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations vary. Power can be approximated by the following formula
[14]
Clock output range, 5 V
operation
Duty cycle for outputs, defined as t
f
Duty cycle for outputs, defined as t
f
Output clock rise time
Output clock fall time
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
Skew delay between any identical or related outputs
16, 20]
Frequency transition rate
OUT
OUT
DD
[14]
=10+0.06•(F
> 66 MHZ
< 66 MHZ
[13]
[13]
I
I
I
I
Except crystal pins
Except crystal pins
V
V
Three-state outputs
V
Shutdown active,
excluding V
CPLL
OH
OL
OH
OL
IN
IN
DD
BATT
= 4.0 mA
= 0.5 mA
= 4.0 mA
= 0.5 mA
= V
= +0.5 V
+F
= V
UPLL
= 3.0 V
DD
[17]
DD
Description
[17]
+2•F
–0.5 V
max., 3.3V operation
BATT
SPLL
Conditions
CY2291
CY2291F
)+0.27•(F
CY2291I/CY2291FI
2
2
 t
 t
CLKA
1
1
[16]
[16]
+F
CLKB
+F
CLKC
[18,
+F
CLKD
(100 MHz)
(90 MHz)
V
+F
Min
2.4
BATT
0.5
2.0
40%
45%
11.1
Min
1.0
CPUCLK
10
+F
CLKF
< 0.25
Typ
< 1
< 1
50%
50%
50
10
Typ
5
2.5
10
10
+F
3
XBUF
(76.923 kHz)
(76.923 kHz)
).
Max
250
100
13000
13000
0.4
0.4
0.8
10
10
70
15
60%
55%
Max
20.0
0.5
15
15
5
4
CY2291
Page 7 of 17
MHz/ms
Unit
mA
A
A
A
A
A
V
V
V
V
V
V
Unit
ns
ns
ns
ns
ns
ns
ns
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