MPC9448AC Freescale Semiconductor, MPC9448AC Datasheet
MPC9448AC
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MPC9448AC Summary of contents
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MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer The MPC9448 is a 3.3V or 2.5V compatible, 1:12 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less ...
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MPC9448 V CC PCLK 0 PCLK CLK STOP CCLK CLK_SEL V CC CLK_STOP SYNC V CC (all input resistors have a value of 25k OE Figure 1. Logic Diagram Table 1. FUNCTION TABLE Control Default CLK_SEL 1 ...
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Table 3. ABSOLUTE MAXIMUM RATINGS* Symbol Parameter V CC Supply Voltage Input Voltage V OUT DC Output Voltage Input Current I OUT DC Output Current T Stor Storage Temperature Range * Absolute maximum continuous ...
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MPC9448 Table 6. AC CHARACTERISTICS ( 3.3V 5 – + Symbol Characteristics f ref Input Frequency f MAX Maximum Output Frequency V PP Peak-to-peak input voltage V CMR b Common Mode ...
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Table 8. AC CHARACTERISTICS ( 2.5V 5 – + Symbol Characteristics f ref Input Frequency f MAX Maximum Output Frequency V PP Peak-to-peak input voltage V CMR b Common Mode Range ...
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MPC9448 Figure 3. Output Clock Stop (CLK_STOP) Timing Diagram CCLK or PCLK CLK_STOP Q0 to Q11 Driving Transmission Lines The MPC9448 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum ...
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Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in ...
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MPC9448 T J,MAX should be selected according to the MTBF system requirements and Table 9. R thja can be derived from Table 10. The R thja represent data based on 1S2P boards, using 2S2P boards will result in a lower ...
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The Following Figures Illustrate the Measurement Reference for the MPC9448 Clock Driver Circuit Pulse Generator Figure 11. CCLK MPC9448 AC Test Reference for 3.3V and 2.5V Differential Pulse Generator W ...
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MPC9448 PCLK V PP PCLK P(LH) t P(HL) Figure 13. Propagation Delay ( Test Reference t SK(LH) The pin–to–pin skew is defined as the worst case difference in propagation delay between any similar delay path ...
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D1 D1/2 PIN 1 INDEX E1 DETAIL D 0.20 C A– 28X SEATING PLANE C DETAIL (S) ...
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MPC9448 Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on ...