MPC9448AC Freescale Semiconductor, MPC9448AC Datasheet - Page 6

• Manufacturer Part Number: MPC9448AC
• Description: IC CLOCK FANOUT BUFF 1:12 32LQFP
• Manufacturer: Freescale Semiconductor
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of MPC9448AC

• Number Of Circuits: 1
• Ratio - Input:output: 2:12
• Differential - Input:output: Yes/No
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Frequency - Max: 350MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 350MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MPC9448
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of 17 (V CC =3.3V), the
outputs can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Motorola application note
AN1091.
point–to–point distribution of signals is the method of choice.
In a point–to–point scheme, either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50
thus only a single terminated line can be driven by each
output of the MPC9448 clock driver.
terminated case, however, there is no DC current draw; thus,
the outputs can drive multiple series terminated lines.
Figure 4 “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9448 clock driver is effectively doubled
due to its capability to drive multiple lines at V CC =3.3V.
CCLK or
PCLK
CLK_STOP
Q0 to Q11
MOTOROLA
IN
IN
The MPC9448 clock driver was designed to drive high
This technique draws a fairly high level of DC current and
Figure 3. Output Clock Stop (CLK_STOP) Timing
Figure 4. Single versus Dual Transmission Lines
MPC9448
MPC9448
OUTPUT
OUTPUT
BUFFER
BUFFER
17
17
In most high performance clock networks,
resistance to V CC 2.
R S = 33
R S = 33
R S = 33
Diagram
Z O = 50
Z O = 50
Z O = 50
For the series
APPLICATIONS INFORMATION
OutA
OutB0
OutB1
6
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases,
the drive capability of the MPC9448 output buffer is more
than sufficient to drive 50 transmission lines on the incident
edge. Note from the delay measurements in the simulations
a delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output–to–output skew
of the MPC9448. The output waveform in Figure 5 “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform; this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 33
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
At the load end the voltage will double, due to the near
3.0
2.5
2.0
1.5
1.0
0.5
The waveform plots in Figure 5 “Single versus Dual Line
0
Figure 5. Single versus Dual Line Termination
t D = 3.8956
2
In
OutA
V L = V S ( Z 0
Z 0 = 50 || 50
R S = 33 || 33
R 0 = 17
V L = 3.0 ( 25
= 1.28V
4
Waveforms
6
series resistor plus the output
TIME (nS)
t D = 3.9386
(R S +R 0 +Z 0 ))
(16.5+17+25)
OutB
8
TIMING SOLUTIONS
10
12
14