ICS85301AKLFT IDT, Integrated Device Technology Inc, ICS85301AKLFT Datasheet - Page 5

• Manufacturer Part Number: ICS85301AKLFT
• Description: IC MUX 2:1 DIFF-LVPECL 16-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Multiplexerr

Specifications of ICS85301AKLFT

• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL
• Output: LVPECL
• Frequency - Max: 3GHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-VFQFN
• Frequency-max: 3GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85301AKLFT

IDT
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
ICS85301
2:1, DIFFERENTIAL-TO-LVPECL MULTIPLEXER
™
/ ICS
™
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
2:1, LVPECL MULTIPLEXER
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
1k
10k
A
O
DDITIVE
FFSET
100k
F
ROM
P
C
HASE
5
ARRIER
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
3.3V or 2.5V @ 622MHz (12kHz to 20MHz)
J
F
ITTER
1M
REQUENCY
(H
Z
)
Additive Phase Jitter
10M
ICS85301 REV. B DECEMBER 22, 2006
= 0.009ps typical
100M