ICS83940DYI-01LFT IDT, Integrated Device Technology Inc, ICS83940DYI-01LFT Datasheet - Page 2

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ICS83940DYI-01LFT

Manufacturer Part Number
ICS83940DYI-01LFT
Description
IC FANOUT BUFFER 1:18 32-LQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet

Specifications of ICS83940DYI-01LFT

Number Of Circuits
1
Ratio - Input:output
2:18
Differential - Input:output
Yes/No
Input
CML, LVCMOS, LVPECL, LVTTL, SSTL
Output
LVCMOS, LVTTL
Frequency - Max
250MHz
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Frequency-max
250MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
83940DYI-01LFT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS83940DYI-01LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
ICS83940I-01 Data Sheet
ICS83940DYI-01 REVISION A SEPTEMBER 27, 2010
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C
R
R
C
R
1, 2, 12, 17, 25
IN
PULLDOWN
PULLUP
PD
OUT
8, 16, 21, 29
13, 14, 15,
18, 19, 20,
22, 23, 24,
26, 27, 28,
30, 31, 32
9, 10, 11,
Number
3
4
5
6
7
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Q17, Q16, Q15,
Q14, Q13, Q12,
LVCMOS_CLK
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
CLK_SEL
nPCLK
Name
PCLK
V
GND
V
DDO
DD
Output
Power
Power
Power
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Test Conditions
Description
Power supply ground.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Clock select input. When HIGH, selects LVCMOS_CLK input. When LOW,
selects PCLK, nPCLK inputs. LVCMOS / LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
Power supply pin.
Output supply pins.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
2
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER
Minimum
17
©2010 Integrated Device Technology, Inc.
Typical
DD
51
51
23
4
9
/2 default when left floating.
Maximum
28
Units
k
k
pF
pF

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