MPC9443AE IDT, Integrated Device Technology Inc, MPC9443AE Datasheet - Page 8

• Manufacturer Part Number: MPC9443AE
• Description: IC CLK FANOUT BUFFER 48-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of MPC9443AE

• Number Of Circuits: 1
• Ratio - Input:output: 3:16
• Differential - Input:output: Yes/No
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Frequency - Max: 350MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Frequency-max: 350MHz
• Number Of Clock Inputs: 3
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS/LVPECL
• Mounting: Surface Mount
• Pin Count: 48
• Quiescent Current: 2mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER
Driving Transmission Lines
signals in a terminated transmission line environment. To provide
the optimum flexibility to the user, the output drivers were
designed to exhibit the lowest impedance possible. With an output
impedance of less than 20 Ω, the drivers can drive either parallel
or series terminated transmission lines at V
information on transmission lines, the reader is referred to
Freescale application note AN1091. In most high performance
clock networks, point-to-point distribution of signals is the method
of choice. In a point-to-point scheme, either series terminated or
parallel terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a 50 Ω
resistance to V
only a single terminated line can be driven by each output of the
MPC9443 clock driver. For the series terminated case, however,
there is no DC current draw; thus, the outputs can drive multiple
series terminated lines.
single series terminated line versus two series terminated lines in
parallel. When taken to its extreme, the fanout of the MPC9443
clock driver is effectively doubled due to its capability to drive
multiple lines (at V
an output driving a single line versus two lines. In both cases, the
drive capability of the MPC9443 output buffer is more than
sufficient to drive 50 Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations, a delta of
only 43 ps exists between the two differently loaded outputs. This
suggests that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the MPC9443. The
output waveform in
step is caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 31 Ω series resistor, plus
the output impedance, does not match the parallel combination of
the line impedances. The voltage wave launched down the two
lines will equal:
IN
IN
MPC9443
2.5V, 3.3V LVCMOS CLOCK FANOUT BUFFER
The MPC9443 clock driver was designed to drive high-speed
This technique draws a fairly high level of DC current ,and thus,
The waveform plots in
Figure 3. Single versus Dual Transmission Lines
MPC9443
MPC9443
Output
Output
Buffer
Buffer
19Ω
19Ω
V
CC
L
÷2.
= V
CC
Figure 4
= 3.3 V).
S
R
R
R
S
S
Figure 3
S
(Z
= 31 Ω
= 31 Ω
= 31 Ω
Figure 4
0
÷ (R
shows a step in the waveform. This
S
illustrates an output driving a
+ R
Z
Z
Z
show the simulation results of
O
O
O
= 50 Ω
= 50 Ω
= 50 Ω
0
+ Z
0
CC
))
= 3.3 V. For more
APPLICATIONS INFORMATION
OutA
OutB0
OutB1
8
reflection coefficient, to 2.52 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in this
case 4.0 ns).
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the situation in
Figure 5
resistors are reduced such that when the parallel combination is
added to the output buffer impedance, the line impedance is
perfectly matched.
At the load end, the voltage will double, due to the near unity
Since this step is well above the threshold region it will not
3.0
2.5
2.0
1.5
1.0
0.5
0
should be used. In this case, the series terminating
Figure 5. Optimized Dual Line Termination
MPC9443
Figure 4. Single versus Dual Waveforms
Output
19Ω
Buffer
t
2
19Ω + 12Ω || 12Ω = 50Ω || 50Ω
D
Z
R
R
V
= 3.8956
OutA
0
L
S
0
In
= 50 Ω || 50 Ω
= 31 Ω || 31 Ω
= 19 Ω
= 3.0 (25 ÷ (15.5 + 19 + 25)
= 1.26 V
4
25Ω = 25Ω
R
R
S
S
MPC9443 REV. 5 SEPTEMBER 19, 2008
= 12 Ω
= 12 Ω
6
Time (ns)
t
D
= 3.9386
OutB
8
Z
Z
O
O
= 50 Ω
= 50 Ω
10
12
14