ICS85354AK-01LF IDT, Integrated Device Technology Inc, ICS85354AK-01LF Datasheet - Page 12

• Manufacturer Part Number: ICS85354AK-01LF
• Description: IC MUX DUAL 2:1 1:2 16-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS85354AK-01LF

• Number Of Circuits: 2
• Ratio - Input:output: 2:1, 1:2
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL
• Output: LVPECL
• Frequency - Max: 2.5GHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-VFQFN
• Frequency-max: 2.5GHz
• Number Of Clock Inputs: 3
• Output Frequency: 2500MHz
• Output Logic Level: ECL/LVPECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: CML/ECL/LVDS/LVPECL
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85354AK-01LF

T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50
85354AK-01
RTT =
ERMINATION FOR
((V
FOUT
F
OH
IGURE
+ V
OL
3A. LVPECL O
) / (V
1
3.3V LVPECL O
CC
Z
Z
– 2)) – 2
transmission lines. Matched imped-
o
o
= 50
= 50
Z
o
50
UTPUT
T
ERMINATION
RTT
UTPUTS
50
PRELIMINARY
V
CC
FIN
- 2V
D
12
IFFERENTIAL
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT
F
IGURE
-
TO
3B. LVPECL O
-LVPECL/ECL M
Z
Z
o
o
= 50
= 50
125
84
ICS85354-01
UTPUT
3.3V
T
125
84
ERMINATION
D
REV. A JANUARY 16, 2008
UAL
ULTIPLEXER
FIN
2:1/1:2