ICS83905AKLF IDT, Integrated Device Technology Inc, ICS83905AKLF Datasheet - Page 13

• Manufacturer Part Number: ICS83905AKLF
• Description: IC FANOUT BUFFER 1:6 20-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution)r

Specifications of ICS83905AKLF

• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: No/No
• Input: Crystal
• Output: LVCMOS, LVTTL
• Frequency - Max: 100MHz
• Voltage - Supply: 1.6 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN, 20-VFQFPN
• Frequency-max: 100MHz
• Number Of Outputs: 6
• Operating Supply Voltage (max): 3.465V
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (min): 1.6V
• Mounting: Surface Mount
• Pin Count: 20
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Package Type: VFQFPN EP
• Input Frequency: 40MHz
• Duty Cycle: 53%
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 83905AKLF

ICS83905 Data Sheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
ICS83905AM REVISION B JULY 20, 2009
PIN PAD
PIN
GROUND PLANE
SOLDER
EXPOSED HEAT SLUG
THERMAL VIA
13
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s
Thermally/Electrically Enhance Leadframe Base Package, Amkor
Technology.
Outputs:
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
LAND PATTERN
(GROUND PAD)
SOLDER
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PIN
©2009 Integrated Device Technology, Inc.
PIN PAD