MPC962309EJ-1HR2 IDT, Integrated Device Technology Inc, MPC962309EJ-1HR2 Datasheet - Page 2

• Manufacturer Part Number: MPC962309EJ-1HR2
• Description: IC BUFFER ZD 1:5 3.3V 16-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of MPC962309EJ-1HR2

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:9
• Differential - Input:output: No/No
• Frequency - Max: 133.33MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 133.33MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ 3.3V ZERO DELAY BUFFER
MPC962305
LOW-COST, 3.3V ZERO DELAY BUFFER
Table 1. Pin Description for MPC962309
Table 2. Pin Description for MPC962305
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
1. Weak pull-down.
2. Weak pull-down on all outputs.
Block Diagram
REF
S2
S1
Pin
Pin
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
CLKOUT
CLKOUT
CLKA1
CLKA2
CLKB1
CLKB2
CLKB3
CLKB4
CLKA3
CLKA4
CLK2
CLK1
CLK3
CLK4
Signal
REF
Signal
REF
GND
S2
S1
GND
GND
V
V
V
DD
DD
DD
PLL
(3)
(3)
(1)
(1)
Select Input
(2)
(2)
(2)
(2)
Decoding
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Input reference frequency, 5 V-tolerant input
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3 V supply
Ground
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
3.3 V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
Input reference frequency, 5 V-tolerant input
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3 V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
MUX
2
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Description
Description
CLKA1
CLKA2
CLKB1
CLKB2
GND
REF
V
CLK2
CLK1
GND
S2
DD
REF
Pin Configuration
1
2
3
4
5
6
7
8
SOIC/TSSOP
SOIC/TSSOP
1
2
3
4
Top View
Top View
MPC962305 REV 7 JULY 16, 2007
16
15
14
13
12
11
10
8
7
6
5
9
CLKOUT
CLK4
V
CLK3
DD
CLKOUT
CLKA4
CLKA3
V
GND
CLKB4
CLKB3
S1
DD