AD9512BCPZ Analog Devices Inc, AD9512BCPZ Datasheet - Page 4

• Manufacturer Part Number: AD9512BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9512BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9512/PCB - BOARD EVAL CLOCK 5CHAN 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9512
SPECIFICATIONS
Typical (Typ) is given for V
values are given over full V
CLOCK INPUTS
Table 1.
Parameter
CLOCK INPUTS (CLK1, CLK2)
1
2
3
CLOCK OUTPUTS
Table 2.
Parameter
LVPECL CLOCK OUTPUTS
LVDS CLOCK OUTPUTS
CMOS CLOCK OUTPUTS
CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input.
With a 50 Ω termination, this is −12.5 dBm.
With a 50 Ω termination, this is +10 dBm.
Input Frequency
Input Sensitivity
Input Common-Mode Voltage, V
Input Common-Mode Range, V
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
OUT0, OUT1, OUT2; Differential
Output Frequency
Output High Voltage (V
Output Low Voltage (V
Output Differential Voltage (V
OUT3, OUT4; Differential
Output Frequency
Differential Output Voltage (V
Delta V
Output Offset Voltage (V
Delta V
Short-Circuit Current (I
OUT3, OUT4
Output Frequency
Output Voltage High (V
Output Voltage Low (V
Input Level
OD
OS
SA
OL
OL
OH
OH
, I
)
)
OS
S
S
)
)
1
SB
and T
)
= 3.3 V ± 5%; T
)
OD
OD
CMR
)
)
A
CM
(−40°C to +85°C) variation.
Min
V
V
660
250
1.125
V
S
S
S
A
Min
0
1.5
1.3
4.0
− 1.22
− 2.10
− 0.1
= 25°C, R
Typ
150
1.6
150
4.8
2
SET
Typ
V
V
810
360
1.23
14
2
S
S
− 0.98
− 1.80
= 4.12 kΩ, unless otherwise noted. Minimum (Min) and Maximum (Max)
Max
1.6
2
1.7
1.8
5.6
Rev. A | Page 4 of 48
3
Unit
GHz
mV p-p
V p-p
V
V
mV p-p
kΩ
pF
Max
1200
V
V
965
800
450
25
1.375
25
24
250
0.1
S
S
− 0.93
− 1.67
Test Conditions/Comments
Jitter performance can be improved with higher slew
rates (greater swing).
Larger swings turn on the protection diodes and can
degrade jitter performance.
Self-biased; enables ac coupling.
With 200 mV p-p signal applied; dc-coupled.
CLK2 ac-coupled; CLK2B ac bypassed to RF ground.
Self-biased.
Unit
MHz
V
V
mV
MHz
mV
mV
V
mV
mA
MHz
V
V
Test Conditions/Comments
Termination = 50 Ω to V
Output level 3Dh (3Eh) (3Fh)<3:2> = 10b
See Figure 14
Termination = 100 Ω differential; default
Output level 40h (41h)<2:1> = 01b
3.5 mA termination current
See Figure 15
Output shorted to GND
Single-ended measurements;
B outputs: inverted, termination open
With 5 pF load each output; see Figure 16
@ 1 mA load
@ 1 mA load
S
− 2 V