AD9512BCPZ Analog Devices Inc, AD9512BCPZ Datasheet - Page 35

• Manufacturer Part Number: AD9512BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9512BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9512/PCB - BOARD EVAL CLOCK 5CHAN 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SCLK
SCLK
SCLK
Table 15. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
R/ W
SCLK
SDIO
SDIO
SDIO
SDIO
CSB
CSB
SDO
CSB
CSB
DON’T CARE
DON’T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
I14
W1
DON'T CARE
R/W
W1
R/W
A0 A1 A2 A3
W0
I13
W0
W1
16-BIT INSTRUCTION HEADER
A12
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
t
W0
S
R/W
I12
A12 = 0
A12
t
A11 A10 A9 A8 A7
DS
A4
W1
16-BIT INSTRUCTION HEADER
16-BIT INSTRUCTION HEADER
A5 A6 A7 A8 A9 A10 A11 A12
Figure 34. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
SCLK
SDIO
SDO
CSB
Figure 32. Serial Control Port Write—MSB First, 16-Bit Instruction, 2 Bytes of Data
Figure 33. Serial Control Port Read—MSB First, 16-Bit Instruction, 4 Bytes of Data
I11
A11 = 0
W0
t
Figure 36. Serial Control Port Write—LSB First, 16-Bit Instruction, 2 Bytes Data
DH
A12
Figure 35. Timing Diagram for Serial Control Port Register Read
A6 A5
I10
A10 = 0
A11
t
HI
DATA BIT N
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
A4 A3 A2
REGISTER (N) DATA
A10
t
LO
t
DV
W0
Rev. A | Page 35 of 48
A9
I9
A9 = 0
t
W1
A1 A0
CLK
R/W
A8
D0
D7 D6 D5 D4 D3
DATA BIT N – 1
I8
A8 = 0
REGISTER (N – 1) DATA
A7
D1
REGISTER (N) DATA
REGISTER (N) DATA
D2 D3 D4
A6
I7
A7 = 0
A5
D2 D1
D5 D6 D7
D4
REGISTER (N – 2) DATA
I6
A6
D0 D7
D3
D0
I5
A5
D6 D5
D1 D2
REGISTER (N – 1) DATA
REGISTER (N + 1) DATA
D2
I4
A4
D4 D3 D2
D3 D4 D5
D1
REGISTER (N – 3) DATA
I3
A3
D0
D1 D0
t
D6
H
I2
A2
D7
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
I1
A1
AD9512
DON'T CARE
DON'T CARE
DON'T CARE
DON'T
CARE
LSB
I0
A0