AD9512BCPZ Analog Devices Inc, AD9512BCPZ Datasheet - Page 2

• Manufacturer Part Number: AD9512BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9512BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9512/PCB - BOARD EVAL CLOCK 5CHAN 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9512
TABLE OF CONTENTS
Specifications..................................................................................... 4
Timing Diagrams............................................................................ 15
Absolute Maximum Ratings.......................................................... 16
Pin Configuration and Function Descriptions........................... 17
Terminology .................................................................................... 19
Typical Performance Characteristics ........................................... 20
Functional Description .................................................................. 24
Clock Inputs .................................................................................. 4
Clock Outputs ............................................................................... 4
Timing Characteristics ................................................................ 5
Clock Output Phase Noise .......................................................... 7
Clock Output Additive Time Jitter........................................... 10
Serial Control Port ..................................................................... 12
FUNCTION Pin ......................................................................... 13
SYNC Status Pin ......................................................................... 13
Power............................................................................................ 14
Thermal Characteristics ............................................................ 16
ESD Caution................................................................................ 16
Overall.......................................................................................... 24
FUNCTION Pin ......................................................................... 24
DSYNC and DSYNCB Pins....................................................... 24
Clock Inputs ................................................................................ 24
Dividers........................................................................................ 25
Delay Block.................................................................................. 30
RESETB: 58h<6:5> = 00b (Default)..................................... 24
SYNCB: 58h<6:5> = 01b ....................................................... 24
PDB: 58h<6:5> = 11b............................................................. 24
Setting the Divide Ratio ........................................................ 25
Setting the Duty Cycle ........................................................... 25
Divider Phase Offset .............................................................. 29
Calculating the Delay............................................................. 30
Rev. A | Page 2 of 48
Serial Control Port ......................................................................... 33
Register Map and Description ...................................................... 37
Power Supply................................................................................... 43
Applications..................................................................................... 44
Outputs ........................................................................................ 30
Power-Down Modes .................................................................. 31
Reset Modes ................................................................................ 31
Single-Chip Synchronization.................................................... 32
Multichip Synchronization ....................................................... 32
Serial Control Port Pin Descriptions....................................... 33
General Operation of Serial Control Port............................... 33
The Instruction Word (16 Bits) ................................................ 34
MSB/LSB First Transfers ........................................................... 34
Summary Table........................................................................... 37
Register Map Description ......................................................... 39
Power Management ................................................................... 43
Using the AD9512 Outputs for ADC Clock Applications.... 44
CMOS Clock Distribution ........................................................ 44
Chip Power-Down or Sleep Mode—PDB........................... 31
Distribution Power-Down .................................................... 31
Individual Clock Output Power-Down............................... 31
Individual Circuit Block Power-Down................................ 31
Power-On Reset—Start-Up Conditions when
VS is Applied........................................................................... 31
Asynchronous Reset via the FUNCTION Pin ................... 31
Soft Reset via the Serial Port................................................. 31
SYNCB—Hardware SYNC ................................................... 32
Soft SYNC—Register 58h<2>............................................... 32
Framing a Communication Cycle with CSB ...................... 33
Communication Cycle—Instruction Plus Data ................. 33
Write ........................................................................................ 33
Read ......................................................................................... 34