ICS854057AGLF IDT, Integrated Device Technology Inc, ICS854057AGLF Datasheet - Page 5

IC CLK MUX HS DIFF LVDS 20-TSSOP

ICS854057AGLF

Manufacturer Part Number
ICS854057AGLF
Description
IC CLK MUX HS DIFF LVDS 20-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Multiplexerr
Datasheet

Specifications of ICS854057AGLF

Number Of Circuits
1
Ratio - Input:output
4:1, 2:1
Differential - Input:output
Yes/Yes
Input
CML, LVDS, LVPECL, SSTL
Output
LVDS
Frequency - Max
2GHz
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Frequency-max
2GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1181
800-1181-5
800-1181
854057AGLF
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
854057AG
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
100
Integrated
Circuit
Systems, Inc.
1k
10k
O
www.icst.com/products/hiperclocks.html
FFSET
A
DDITIVE
F
ROM
100k
C
ARRIER
P
HASE
5
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
F
REQUENCY
1M
J
4:1
ITTER
Additive Phase Jitter
OR
WITH
(H
2:1 LVDS C
Z
)
10M
I
NTERNAL
(12kHz to 20MHz)
100M
@ 622.08MHz
= 66fs typical
I
LOCK
NPUT
ICS854057
REV. A OCTOBER 29, 2008
M
T
ERMINATION
ULTIPLEXER
500M

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