ICS83905AGLF IDT, Integrated Device Technology Inc, ICS83905AGLF Datasheet - Page 18

IC FANOUT BUFFER 1:6 16-TSSOP

ICS83905AGLF

Manufacturer Part Number
ICS83905AGLF
Description
IC FANOUT BUFFER 1:6 16-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution)r
Datasheet

Specifications of ICS83905AGLF

Number Of Circuits
1
Ratio - Input:output
1:6
Differential - Input:output
No/No
Input
Crystal
Output
LVCMOS, LVTTL
Frequency - Max
100MHz
Voltage - Supply
1.6 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Frequency-max
100MHz
Number Of Outputs
6
Operating Supply Voltage (max)
3.465V
Operating Temp Range
0C to 70C
Operating Supply Voltage (min)
1.6V
Mounting
Surface Mount
Pin Count
16
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Package Type
TSSOP
Input Frequency
40MHz
Duty Cycle
53%
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1115
800-1115-5
800-1115
83905AGLF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS83905AGLF
Manufacturer:
IDT
Quantity:
178
Part Number:
ICS83905AGLFT
Manufacturer:
IDT
Quantity:
20 000
ICS83905 Data Sheet
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
Table 9C. Package Dimensions
Reference Document: JEDEC Publication 95, MO-220
ICS83905AM REVISION B JULY 20, 2009
N
D2 & E2
Symbol
D & E
D
A1
A3
N
A
b
& N
L
e
Ind ex Area
E
All Dimensions in Millimeters
JEDEC Variation: VGGD-1/-5
0.6 x 0.6 max
OPTIONAL
Chamfer 4x
Minimum
0.80
0.18
1.95
0.35
N
0
To p View
D
4.00 Basic
0.50 Basic
Nominal
0.25 Ref.
20
5
S eating Plan e
Singula tion
Maximum
Anvil
OR
1.00
0.05
0.30
2.25
0.75
0. 08
A1
C
A
A 3
E 2
C
E2
N & N
(Ref.)
Odd
L
2
18
e
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9C below.
(N
-1)x e
(R ef.)
D2
D2
2
N
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
1
2
N & N
Even
(Ref.)
e
Th er mal
2
Ba se
If N & N
are Even
(N -1)x e
b
(Ty p.)
(Re f.)
©2009 Integrated Device Technology, Inc.

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