ICS8547AY IDT, Integrated Device Technology Inc, ICS8547AY Datasheet
ICS8547AY
Specifications of ICS8547AY
8547AY
Related parts for ICS8547AY
ICS8547AY Summary of contents
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... CLK1 nCLK1 CLK2 nCLK2 CLK3 nCLK3 CLK4 nCLK4 CLK5 nCLK5 ICS8547AY D IFFERENTIAL F EATURES 12 LVDS outputs Selectable CLKx, nCLKx inputs CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Maximum output frequency: 700MHz Translates any differential input signal (LVPECL, LVHSTL, ...
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... ABLE IN ESCRIPTIONS ICS8547AY D IFFERENTIAL www.icst.com/products/hiperclocks.html 2 ICS8547 KEW - -LVDS C TO LOCK REV. A FEBRUARY 4, 2003 , UFFERS ...
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... ABLE IN HARACTERISTICS ABLE LOCK NPUT UNCTION ABLE ICS8547AY D IFFERENTIAL " www.icst.com/products/hiperclocks.html 3 ICS8547 KEW - -LVDS LOCK REV. A FEBRUARY 4, 2003 -2 TO UFFERS " ...
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... ICS8547AY D IFFERENTIAL 4.6V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the -0. 0 device. These ratings are stress specifications only. Functional -0. 0.5V operation of product at these conditions or any conditions be- DDO yond those listed in the DC Characteristics or AC Character- 47.9° ...
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... ABLE HARACTERISTICS ICS8547AY D IFFERENTIAL = 3.3V±5 0°C 85° DDO ƒ ƒ < ƒ www.icst.com/products/hiperclocks.html 5 ICS8547 KEW - -LVDS LOCK REV. A FEBRUARY 4, 2003 , UFFERS ...
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... QxA, nQxA QxA, nQxA QxB, nQxB QxB, nQxB tsk( ANK KEW nQxA, nQxB QxA, QxB Pulse Width t PERIOD t PW odc = t PERIOD odc & ERIOD ICS8547AY D IFFERENTIAL M I EASUREMENT NFORMATION V DD nCLKx SCOPE CLKx nQx GND D I IFFERENTIAL NPUT nQx Qx nQy Qy tsk(o) ...
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... V DD LVDS DC Input / VOD ETUP LVDS DC Input I S ETUP OS LVDS I S ETUP OFF ICS8547AY D IFFERENTIAL V DD out LVDS 100 Input OD OD out / VOS ETUP out I OS LVDS DC Input I OSB out I S ETUP OSD OFF www.icst.com/products/hiperclocks.html 7 ICS8547 KEW TO - -LVDS LOCK UFFERS out ...
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... NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio F IGURE ICS8547AY D IFFERENTIAL A I PPLICATION NFORMATION ...
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... S CLK/ CLK I IGURE I ER LOCK N 3.3V LVPECL D RIVER ICS8547AY D IFFERENTIAL examples only. Please consult with the vendor of the driver com- and V must meet the ponent to confirm the driver termination requirements. For ex- OH ample in Figure 2, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation ...
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... NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS8547 is: 1117 ICS8547AY D IFFERENTIAL line environment. For buffer with multiple LDVS driver rec- single) transmission ommended to terminate the unused outputs. ...
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... ACKAGE UTLINE UFFIX ABLE Reference Document: JEDEC Publication 95, MS-026 ICS8547AY D IFFERENTIAL D ACKAGE IMENSIONS ° www.icst.com/products/hiperclocks.html 11 ICS8547 KEW - -LVDS C TO LOCK ° REV. A FEBRUARY 4, 2003 , UFFERS ...
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... Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS8547AY D IFFERENTIAL ...