ICS83026AMILF IDT, Integrated Device Technology Inc, ICS83026AMILF Datasheet

IC FANOUT BUFFER 1:2 DIFF 8-SOIC

ICS83026AMILF

Manufacturer Part Number
ICS83026AMILF
Description
IC FANOUT BUFFER 1:2 DIFF 8-SOIC
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution)r
Datasheet

Specifications of ICS83026AMILF

Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
Yes/No
Input
HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
LVCMOS, LVTTL
Frequency - Max
350MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC
Frequency-max
350MHz
Number Of Outputs
2
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Propagation Delay Time
2.5ns
Operating Supply Voltage (min)
3V
Mounting
Surface Mount
Pin Count
8
Operating Supply Voltage (typ)
3.3V
Package Type
SOIC N
Duty Cycle
60%
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1103
800-1103-5
800-1103
83026AMILF

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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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ICS83026AMI REVISION C AUGUST 26, 2009
General Description
LVPECL, SSTL, and HCSL) and translate to two single-ended
LVCMOS/LVTTL outputs with a maximum output skew of 20ps. The
small 8-lead SOIC footprint makes this device ideal for use in
applications with limited board space.
Block Diagram
nCLK
HiPerClockS™
CLK
ICS
Pulldown
Pullup
The ICS83026I is a low skew, 1-to-2 Differential-to-
LVCMOS/LVTTL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from IDT.The differential input can accept
most differential signal types (LVDS, LVHSTL,
Low Skew, 1-to-2,
Differential-to-LVCMOS/LVTTL Fanout Buffer
Q0
Q1
1
Features
Two LVCMOS/LVTTL outputs
Differential CLK/nCLK input pair
CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency: 350MHz (typical)
Output skew: 20ps (maximum)
Part-to-part skew: 600ps (maximum)
Additive phase jitter, RMS: 0.092ps (typical)
Small 8 lead SOIC package saves board space
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
3.9mm x 4.9mm x 1.375mm package body
Pin Assignment
8-Lead SOIC, 150Mil
nCLK
CLK
nc
nc
M Package
ICS83026I
Top View
1
2
3
4
©2009 Integrated Device Technology, Inc.
8
7
6
5
V
Q0
Q1
GND
DD
ICS83026I
DATA SHEET

Related parts for ICS83026AMILF

ICS83026AMILF Summary of contents

Page 1

Low Skew, 1-to-2, Differential-to-LVCMOS/LVTTL Fanout Buffer General Description The ICS83026I is a low skew, 1-to-2 Differential-to- ICS LVCMOS/LVTTL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock HiPerClockS™ Solutions from IDT.The differential input can accept most ...

Page 2

ICS83026I Data Sheet Table 1. Pin Descriptions Number Name Unused 2 CLK Input 3 nCLK Input 5 GND Power 6 Q1 Output 7 Q0 Output 8 V Power DD NOTE: Pullup and Pulldown refer to internal input ...

Page 3

ICS83026I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those ...

Page 4

ICS83026I Data Sheet AC Electrical Characteristics Table 4. AC Characteristics Symbol Parameter f Output Frequency MAX t Propagation Delay, NOTE 1 PD tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Part-to-Part Skew; NOTE 3, 4 Buffer Additive Phase Jitter, ...

Page 5

ICS83026I Data Sheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase ...

Page 6

ICS83026I Data Sheet Parameter Measurement Information 1.65V±0.15V V DD LVCMOS GND -1.65V±0.15V 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit tsk(o) Output Skew Q0 PERIOD t PW odc ...

Page 7

ICS83026I Data Sheet Parameter Measurement Information, continued nCLK CLK Q0 Propagation Delay Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 1 shows how the differential input can be wired to ...

Page 8

ICS83026I Data Sheet Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the V input requirements. Figures show interface examples for the HiPerClockS CLK/nCLK input ...

Page 9

ICS83026I Data Sheet Reliability Information θ Table 5. vs. Air Flow Table for an 8 Lead SOIC JA Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS83026I is: 416 Pin-to-pin compatible with ...

Page 10

ICS83026I Data Sheet Ordering Information Table 7. Ordering Information Part/Order Number Marking 83026AMI 83026AMI 83026AMIT 83026AMI 83026AMILF 83026AIL 83026AMILFT 83026AIL NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS ...

Page 11

ICS83026I Data Sheet Revision History Sheet Rev Table Page Description of Change A 1 Revised General Description. 1 Features Section - added Lead-Free bullet Pin Characteristics Table - changed Added Application Information ...

Page 12

ICS83026I Data Sheet 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications ...

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