STCD1020RDG6F STMicroelectronics, STCD1020RDG6F Datasheet - Page 17

IC CLK DISTRIB 2CH 2.8V 8-TDFN

STCD1020RDG6F

Manufacturer Part Number
STCD1020RDG6F
Description
IC CLK DISTRIB 2CH 2.8V 8-TDFN
Manufacturer
STMicroelectronics
Type
Fanout Buffer (Distribution)r
Datasheet

Specifications of STCD1020RDG6F

Number Of Circuits
1
Ratio - Input:output
1:4
Differential - Input:output
No/No
Input
Clock
Output
Clock
Frequency - Max
52MHz
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-TDFN
Frequency-max
52MHz
Number Of Outputs
4
Max Input Freq
52 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8361-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STCD1020RDG6F
Manufacturer:
ON
Quantity:
1 000
STCD1020, STCD1030, STCD1040
Table 7.
1. Valid for ambient operating temperature: T
2.
3. Simulated and determined via design and NOT 100% tested.
4. The quiescent current is measured when the enable pins are active, but without input master clock signal (fmclk = 0 Hz).
5. The active current is dependent on the master clock input Vpp and frequency and the capacitive load condition. The typical
6. The rise time is measured when clock edge transfers from 10% V
7. Other test results are under test condition V
8. Guaranteed with the supply noise of 30 µ Vrms from 300 Hz to 50 kHz.
Table 8.
Table 9.
Symbol
V
Output clock voltage (CLK1…CLK4)
Device enable voltage (EN1…EN4)
Ambient operating temperature (T
t
Symbol
t
CC
RECC
RECB
f
P
C
R
Load capacitance = 10 pF (except where noted).
test condition is 26 MHz sine wave with 1 Vpp master clock input, C
edge transfers from 90% V
MCLK
Vout
V
Clock input voltage level should not exceed supply rails.
Vin
N
I
L
L
CC
supply
Q
Additive phase noise
Buffer recovery time from off to on
STCD10x0 active recovery time
from standby to active
Capacitive load for each channel
Resistive load for each channel
Master clock (eg. from VCTCXO)
Supply voltage
Input clock voltage level
Output gain level
Quiescent current
DC and AC characteristics (1.8 V supply)
Operating and AC measurement conditions (2.8 V supply)
DC and AC characteristics (2.8 V supply)
Parameter
Parameter
Parameter
CC
(3)
to 10% V
(4)
(3)(8)
A
)
(2)
CC
.
A
ENH
= –40 °C to 85 °C; V
= 1.8 V and V
Doc ID 13823 Rev 6
Sine wave/square wave
STCD10x0 active
at 100 kHz offset
at 10 kHz offset
at 1 kHz offset
2 buffers version
3 buffers version
4 buffers version
Condition
ENL
Condition
–40 to +85
C
Condition
2.5 to 3.6
0 to V
0 to V
CC
L
CC
= 0 V.
= 10 pF
L
= 1.65 V to 2.75 V; typical T
to 90% V
= 10 pF.
CC
CC
(1)
(1)
CC
. The fall time is measured when clock
Min
0.75
–1.5
Min
10
2.5
10
DC and AC parameters
A
= 25 °C;
–135
–145
–150
Typ
20
50
10
–0.5
Typ
2.8
1.7
2.2
2.8
26
1
Unit
°
V
V
V
C
Max
Max
20
3.6
2.6
3.3
52
4
Unit
dBc/
MHz
Unit
17/40
Vpp
mA
Hz
pF
dB
µs
µs
V

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