STCD1020RDG6F STMicroelectronics, STCD1020RDG6F Datasheet
STCD1020RDG6F
Specifications of STCD1020RDG6F
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STCD1020RDG6F Summary of contents
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Features ■ outputs buffered clock distribution ■ Single-ended sine wave or square wave clock input and output ■ Individual clock enable for each output ■ Lower fan-out on clock source ■ coupling capacitor needed ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STCD1020, STCD1030, STCD1040 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STCD1020, STCD1030, STCD1040 Figure 30. STCD10x0 recovery time from standby to active (STCD1040, 1.8 V version, EN2=EN3=EN4=0, measure CLK1 when EN1 from ...
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Description 1 Description The STCD1020, STCD1030 and STCD1040 are outputs unity gain clock distribution circuits, which are used to provide a common frequency clock to multimode mobile RF applications. It can also be used for those ...
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STCD1020, STCD1030, STCD1040 2 Device overview Figure 1. Logic diagram Note: No EN3, EN4, CLK3 nor CLK4 for STCD1020 and no EN4 nor CLK4 for STCD1030. Figure 2. Connections diagram (STCD1020, 2-channel MCLK STCD1040 EN1 EN2 Clock distribution ...
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Device overview Figure 3. Connections diagram (STCD1030, 3-channel) Figure 4. Connections diagram (STCD1040, 4-channel) 8/ MCLK STCK1030 EN1 3 TDFN10 EN2 4 EN3 MCLK STCD1040 3 EN1 TDFN12 4 EN2 5 ...
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STCD1020, STCD1030, STCD1040 Table 2. Pin names and functions Pin CLK1, CLK2, CLK3, CLK4 EN1, EN2, EN3, EN4 MCLK V CC GND NC Figure 5. Block diagram Type Clock output channel #1, #2, #3, #4. A 0.001 µF DC cut ...
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Device overview Figure 6. Hardware hookup 10/ EN4 CLK4 STCD1040 EN3 Master MCLK CLK3 Clock input EN2 CLK2 EN1 CLK1 GND Doc ID 13823 Rev 6 STCD1020, STCD1030, STCD1040 Clock enable control Clock #4 output Clock ...
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STCD1020, STCD1030, STCD1040 3 Device operation The STCD1020, STCD1030 and STCD1040 are buffered unity gain clock distribution circuits. They accept the clock input from an external clock source and send buffered outputs ...
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Application information 4 Application information 4.1 Typical applications The STCD1020, STCD1030 and STCD1040 distribute a source clock (for example, from VCTCXO channel outputs. The typical application circuits using STCD1040 are shown in Figure 7 In ...
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STCD1020, STCD1030, STCD1040 Figure 8. Typical application circuit using STCD1040 for baseband peripherals in mobile phone 4.2 Connection of the source clock to MCLK If the output of the clock source voltage level is within the supply rails of the ...
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Application information of the STCD1020, STCD1030 and STCD1040. The proper DC voltage is around half of the supply. The connection of the DC-CUT capacitor and bias for the STCD1020, STCD1030 and STCD1040 is only needed when the output of VCTCXO ...
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STCD1020, STCD1030, STCD1040 5 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any ...
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DC and AC parameters 6 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests ...
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STCD1020, STCD1030, STCD1040 Table 7. DC and AC characteristics (1.8 V supply) Symbol Parameter (3)(8) P Additive phase noise N t Buffer recovery time from off to on RECB STCD10x0 active recovery time t RECC from standby to active C ...
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DC and AC parameters Table 9. DC and AC characteristics (2.8 V supply) (continued) Symbol Parameter (5) I Active current ACT I Standby current SB R Input resistance IN C Input capacitance IN (6) t Rise/fall times r/f (3) BW ...
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STCD1020, STCD1030, STCD1040 7 Typical operating characteristics Typical operating characteristics of STCD1040 are V load capacitance = 10 pF, 26 MHz TCXO ENE3127B from NDK (except where noted). Figure 11. Quiescent current (I EN1=EN2=EN3=EN4=1, no master clock input) Figure 12. ...
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Typical operating characteristics Figure 13. Standby current (I EN1=EN2=EN3=EN4=0, no master clock input) Figure 14. Active current (I EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input from TCXO) 20/40 ) vs. supply voltage ( 0.5 0 -0.5 -1 ...
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STCD1020, STCD1030, STCD1040 Figure 15. Active current (I (STCD1040, 2.8 V version, EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input) Figure 16. Active current (I EN1=EN2=EN3=EN4=1, master clock input Vpp = vs. master clock input voltage level ...
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Typical operating characteristics Figure 17. STCD10x0 recovery time from standby to active (STCD1040, 2.8 V version, EN2=EN3=EN4=0, measure CLK1 when EN1 from Figure 18. STCD10x0 buffer recovery time from off to on (STCD1040, 2.8 V version, EN2=EN3=EN4=1, ...
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STCD1020, STCD1030, STCD1040 Figure 19. Sine wave input clock vs. output clock (STCD1040, 2.8 V version, 26 MHz sine wave master clock input from TCXO) Figure 20. Rise and fall time for square wave output (STCD1040, 2 MHz ...
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Typical operating characteristics Figure 21. Input clock phase noise (STCD1040, 2.8 V version, 26 MHz master clock input from TCXO) Figure 22. Output clock phase noise (STCD1040, 2.8V version, this phase noise includes the additive phase noise from TCXO and ...
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STCD1020, STCD1030, STCD1040 Figure 23. Clock bandwidth (STCD1040, 2.8 V version, C Figure 24. Quiescent current (I EN1=EN2=EN3=EN4=1, no master clock input) Figure 25. Quiescent current (I EN1=EN2=EN3=EN4=1, C 0.00 -1.00 -2.00 -3.00 -4.00 -5.00 -6.00 -7.00 -8. ...
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Typical operating characteristics Figure 26. Standby current (I EN1=EN2=EN3=EN4=0, no master clock input) Figure 27. Active current (I EN1=EN2=EN3=EN4=1, 26 MHz sine wave master clock input from TCXO) Figure 28. Active current (I (STCD1040, 1.8 V version, EN1=EN2=EN3=EN4=1, 26 MHz ...
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STCD1020, STCD1030, STCD1040 Figure 29. Active current (I EN1=EN2=EN3=EN4=1, master clock input Vpp=1 V) Figure 30. STCD10x0 recovery time from standby to active (STCD1040, 1.8 V version, EN2=EN3=EN4=0, measure CLK1 when EN1 from vs. input frequency ...
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Typical operating characteristics Figure 31. STCD10x0 buffer recovery time from off to on (STCD1040, 1.8 V version, EN2 =EN3=EN4=1, measure CLK1 when EN1 from Figure 32. Sine wave input clock vs. output clock (STCD1040, 1.8 V version, ...
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STCD1020, STCD1030, STCD1040 Figure 33. Rise and fall time for square wave output (STCD1040, 1.8 V version, 10 MHz square wave master clock input, C Figure 34. Input clock phase noise (STCD1040, 1.8 V version, 26 MHz master clock input ...
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Typical operating characteristics Figure 35. Output clock phase noise (STCD1040, 1.8 V version, this phase noise includes the additive phase noise from TCXO and STCD1040) Figure 36. Clock bandwidth (STCD1040, 1.8 V version -0.5 -1 -1.5 -2 -2.5 ...
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STCD1020, STCD1030, STCD1040 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available ...
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Package mechanical data Figure 37. TDFN - 8-lead package outline Table 10. TDFN - 8-lead ( mm) package mechanical data Symbol Min. A 0.70 A1 0. 0.45 32/40 ...
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STCD1020, STCD1030, STCD1040 Figure 38. TDFN - 10-lead 2.5 mm package outline Table 11. TDFN - 10-lead (2 x 2.5 mm) package mechanical data Symbol Min. A 0.70 A1 0. 0.45 D ...
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Package mechanical data Figure 39. TDFN - 12-lead package outline Table 12. TDFN - 12-lead ( mm) package mechanical data Symbol Min. A 0.70 A1 0. 0.45 34/40 ...
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STCD1020, STCD1030, STCD1040 Figure 40. Carrier tape for TDFN8, TDFN10, and TDFN12 packages T TOP COVER TAPE K 0 Table 13. Carrier tape dimensions for TDFN8, TDFN10, and TDFN12 packages Package 1.50 8.00 1.75 TDFN8 +0.30/ +0.10/ ...
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Package mechanical data Figure 41. DG package topside marking information (TDFN8) 1. Traceability codes PP = Assembly plant Y = Assembly year WW = Assembly week Figure 42. DH and DM package topside marking information (TDFN10 and TDFN12) 1. Traceability ...
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STCD1020, STCD1030, STCD1040 Figure 43. Landing pattern – TDFN8 mm, TDFN10 2 x 2.5 mm, TDFN12 Table 15. Landing pattern parameters (TDFN8, TDFN10, TDFN12) Parameter L Contact length b Contact width ...
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Part numbering 9 Part numbering Table 16. Ordering information scheme Example: Device type STCD = clock distribution Channels 1020 = 2-channel (1) 1030 = 3-channel 1040 = 4-channel Operating voltage R = 2.5 to 3 1.65 ...
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STCD1020, STCD1030, STCD1040 10 Revision history Table 17. Document revision history Date 08-Aug-2007 08-Oct-2007 03-Apr-2008 08-May-2008 07-Sep-2009 14-May-2010 Revision 1 Initial release. Addition of footnote supply); updated Vout in Updated cover page, 3 15, 16, 17, 18, ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...