SI5017-BM Silicon Laboratories Inc, SI5017-BM Datasheet
SI5017-BM
Specifications of SI5017-BM
Related parts for SI5017-BM
SI5017-BM Summary of contents
Page 1
... PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5017 represents a new standard in low jitter, low power, small size, and integration for high-speed LA/CDRs. It operates from a 3.3 V supply over the industrial temperature range (– °C). ...
Page 2
... Si5017 2 Rev. 1.2 ...
Page 3
... Bit-Error-Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pin Descriptions: Si5017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Rev. 1.2 Si5017 Page 3 ...
Page 4
... Si5017 Detailed Block Diagram LOS BER_LVL Signal LOS_LVL Detect DIN+ Limiting Amp Detector DIN+ Slicing SLICE_LVL Control REFCLK± (optional) Bias REXT Generation 4 LTR BER_ALM BER Monitor Phase A/D DSP VCO n Lock Detection Rev. 1.2 DSQLCH DOUT+ Retime DOUT– CLKOUT+ ...
Page 5
... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5017 specifications are guaranteed when using the recommended application circuit (including component tolerance) of the "Typical Application Schematic" on page 11. ...
Page 6
... Si5017 DOUT CLK OUT DOUT, CLKOUT Figure 3. DOUT and CLKOUT Rise/Fall Times RESET/Cal LOL DATAIN LOL DATAIN LOS Cf-D C r-D Figure 2. Clock to Data Timing Figure 4. PLL Acquisition Time t LOS Figure 5. LOS Response Time Rev. 1.2 80% 20% LOS Threshold Level ...
Page 7
... Load V OCM Line-to-Line 100 Ω Load V OCM Line-to-Line R Single-ended OUT Rev. 1.2 Si5017 Min Typ Max Unit — 163 174 mA — 160 170 — 538 603 mW — 528 554 1.40 1.50 1.60 V 1.90 2.10 2. — 500 mV 10 — 1000 ...
Page 8
... Si5017 Table 3. AC Characteristics (Clock and Data 3.3 V ±5 – ° Parameter Output Clock Rate Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Output Data Rise Time Output Data Fall Time Clock to Data Delay FEC (2.7 Gbps) ...
Page 9
... GEN(PP) J OC- After falling edge of AQ RESET/CAL From the return of valid data T After falling edge of AQ RESET/CAL From the return of valid data C TOL Rev. 1.2 Si5017 Min Typ Max Unit 40 — — — — — — 0.5 — ...
Page 10
... Si5017 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 k Ω ) Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet ...
Page 11
... Loss-of-Signal Indicator Control Inputs Loss-of-Lock Indicator DIN+ DIN– Si5017 REFCLK+ CLKOUT+ REFCLK– CLKOUT– 100 kΩ VDD (1%) 0.1 µF Data Slice Level Set Bit Error Rate Level Set Rev. 1.2 Si5017 Indicator DOUT+ Recovered Data DOUT– Recovered Clock 11 ...
Page 12
... DSPLL, minimizes the acquisition time, and maintains a stable output clock (CLKOUT) when lock-to-reference (LTR) is asserted. When the reference clock is present, the Si5017 uses the reference clock to center the VCO output frequency so that clock and data are recovered from the input data stream ...
Page 13
... This produces a stable output clock as long as supply 128 and temperature are constant. Loss-of-Signal 32 The Si5017 indicates a loss-of-signal condition on the 16 LOS output pin when the input peak-to-peak signal level on DIN falls below an externally controlled threshold. The LOS threshold range is specified in Table 3 and is set by applying a voltage on the LOS_LVL pin ...
Page 14
... SONET/SDH equipment by Bellcore GR-253-CORE, Issue 3, September 2000 and ITU-T G.958. Jitter Tolerance The Si5017’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 8. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device ...
Page 15
... Slope Device Grounding The Si5017 uses the GND pad on the bottom of the 28- pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figure 15 on page 19 and Figure 16 on page 23 for the ground (GND) pad location ...
Page 16
... Figure 11. Input Termination for DIN (ac coupled) 16 Si5017 2.5 V (±5%) 2.5 kΩ Ω RFCLK + 10 kΩ 2.5 kΩ 100 Ω Ω RFCLK – 10 kΩ GND Si5017 2.5 V (±5 Ω DIN+ 50 Ω 50 Ω Ω DIN– GND Rev. 1.2 5 kΩ 7.5 kΩ ...
Page 17
... Figure 13. Single-Ended Input Termination for DIN (ac coupled) Si5017 2.5 V (±5%) 2.5 kΩ RFCLK + 10 kΩ 2.5 kΩ RFCLK – 10 kΩ GND Si5017 2.5 V (±5%) DIN+ 50 Ω 5 kΩ Ω 50 Ω 7.5 kΩ DIN– GND Rev. 1.2 Si5017 17 ...
Page 18
... Si5017 Differential Output Circuitry The Si5017 utilizes a CML architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 14. In applications in which direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is specified in Table 2 on page 7 ...
Page 19
... REFCLK– DOUT– TDI LOL Figure 15. Si5017 Pin Configuration Table 8. Si5017 Pin Descriptions I/O Signal Level 3.3 V Supply Voltage. Nominally 3 LOS Level Control. The LOS threshold is set by the input voltage level applied to this pin. Figure 6 on page 13 shows the input setting to output threshold mapping. ...
Page 20
... Si5017 Table 8. Si5017 Pin Descriptions (Continued) Pin # Pin Name 7 LOL 8 LTR 9 LOS 10 DSQLCH 12 DIN+ 13 DIN– 15 GND 16 DOUT– 17 DOUT+ 19 RESET/CAL 20 I/O Signal Level O LVTTL Loss-of-Lock. This output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 9 ...
Page 21
... Table 8. Si5017 Pin Descriptions (Continued) Pin # Pin Name I/O 20 REXT 22 CLKOUT– 23 CLKOUT+ 24 CLKDSBL 26 BER_LVL 27 BER_ALM 28 NC GND Pad GND Signal Level External Bias Resistor. This resistor is used to establish internal bias cur- rents within the device. This pin must be connected to GND through a 10 kΩ (1%) resistor. ...
Page 22
... Si5017 Ordering Guide Part Number Si5017-BM 22 Package Voltage 28-Lead MLP 3.3 Rev. 1.2 Temperature – °C ...
Page 23
... Package Outline Figure 16 illustrates the package details for the Si5017. Table 9 lists the values for the dimensions shown in the illustration D TOP VIEW Figure 16. 28-Lead Micro Leaded Package (MLP θ SEATING PLANE SECTION "C–C" e SCALE: NONE Table 9. Package Diagram Dimensions ...
Page 24
... Si5017 Document Change List Revision 0.1 to Revision 1.0 ! Added Figure 4, “PLL Acquisition Time,” on page 6. ! Table 2 on page 7 Added FEC (2.7 GHz) Supply Current " Updated values: Supply Current " Added FEC (2.7 GHz) Power Dissipation " Updated values: Power Dissipation " ...
Page 25
... Notes: Rev. 1.2 Si5017 25 ...
Page 26
... Si5017 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...