SI5368B-C-GQR Silicon Laboratories Inc, SI5368B-C-GQR Datasheet - Page 64

• Manufacturer Part Number: SI5368B-C-GQR
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368B-C-GQR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5368
Reset value = 0000 0000
64
Register 136.
Name RST_REG
Type
Bit
5:2
1:0
Bit
7
6
GRADE_RO
RST_REG
Reserved
R/W
Name
D7
ICAL
[1:0]
RST_REG.
Internal Reset.
0: Normal operation.
1: Reset of all internal logic. Outputs tristated or disabled during reset.
ICAL.
Start an Internal Calibration Sequence.
For proper operation, the device must go through an internal calibration sequence. ICAL
is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibration is
complete once the LOL alarm goes low. A valid stable clock (within 100 ppm) must be
present to begin ICAL.
Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take effect.
0: Normal operation.
1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-
calibration, ICAL is internally reset to zero.
Reserved.
GRADE_RO [1:0].
Indicates maximum clock output frequency of this device. Limits the range of the N1_HS
divider.
00: N1_HS x NCn_LS > 4. Maximum clock output frequency = 1.4175 GHz.
01: N1_HS x NCn_LS > 6. Maximum clock output frequency = 808 MHz.
10: N1_HS x NCn_LS > 14. Maximum clock output frequency = 346 MHz.
11: N1_HS x NCn_LS > 20. Maximum clock output frequency = 243 MHz.
ICAL
R/W
D6
Changes in SFOUTn_REG, PD_CKn, or DSBLn_REG will cause a random change in skew
until an ICAL is completed.
D5
Preliminary Rev. 0.41
D4
Reserved
R
Function
D3
D2
GRADE_RO [1:0]
D1
R
D0