SI5368B-C-GQR Silicon Laboratories Inc, SI5368B-C-GQR Datasheet - Page 4

• Manufacturer Part Number: SI5368B-C-GQR
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368B-C-GQR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5368
Table 1. Performance Specifications
(V
4
Temperature Range
Supply Voltage
Supply Current
(Supply current is
independent of V
Input Clock Frequency
(CKIN1, CKIN2, CKIN3,
CKIN4)
Input Clock Frequency
(CKIN3, CKIN4 used as
FSYNC inputs)
Output Clock Frequency
(CKOUT1, CKOUT2,
CKOUT3, CKOUT4, CKOUT5
used as fifth high-speed out-
put)
CKOUT5 used as frame sync
output (FS_OUT)
3-Level Input Pins
Input Mid Current
Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4)
Differential Voltage Swing
Notes:
DD
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
3. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
= 1.8 ±5%, 2.5 V ±10%, or 3.3 V ±10%, T
Clock Family Reference Manual. This document can be downloaded from
Documentation)
Manual. In most designs, an external resistor voltage divider is recommended.
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they
are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled. When
there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
Parameter
DD
)
.
CKN
Symbol
CK
CK
V
CK
CK
I
I
IMM
T
DD
DD
A
OF
OF
DPP
F
F
A
determine PLL divider settings
multiplication ratio determined
All CKOUTs enabled LVPECL
frequency/clock multiplication
www.silabs.com/timing
= –40 to 85 ºC)
by programming device PLL
Rate Precision Clock Family
software DSPLLsim or Any-
Laboratories configuration
Input frequency and clock
dividers. Consult Silicon
Only CKOUT1 enabled
Only CKOUT1 enabled
Preliminary Rev. 0.41
on Documentation) to
Reference Manual at
CMOS format output
All CKOUTs enabled
f
OUT
f
ratio combination.
OUT
for a given input
Test Condition
format output
See Note 3.
Sleep Mode
See Note 2.
= 622.08 MHz
= 19.44 MHz
(click
www.silabs.com/timing
0.002
0.002
0.002
0.002
1213
2.97
2.25
1.71
0.25
Min
–40
970
—
—
—
—
—
–2
Typ
394
253
278
229
165
3.3
2.5
1.8
25
—
—
—
—
—
—
—
—
(click on
0.512
1400
1134
Max
3.63
2.75
1.89
284
261
435
321
710
945
710
85
—
2
Unit
MHz
MHz
MHz
MHz
V
mA
mA
mA
mA
mA
µA
ºC
V
V
V
PP