SI5368B-C-GQR Silicon Laboratories Inc, SI5368B-C-GQR Datasheet - Page 5

• Manufacturer Part Number: SI5368B-C-GQR
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368B-C-GQR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. Performance Specifications (Continued)
(V
Input Voltage Level Limits
Common Mode Voltage
Rise/Fall Time
Duty Cycle
(Minimum Pulse Width)
Output Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5/FS_OUT)
Common Mode
Differential Output Swing
Single Ended Output Swing
PLL Performance
Jitter Generation
Jitter Peaking
Phase Noise
Subharmonic Noise
Spurious Noise
Notes:
DD
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
3. The LVPECL and CMOS output formats draw more current than either LVDS or CML; however, there are restrictions in
= 1.8 ±5%, 2.5 V ±10%, or 3.3 V ±10%, T
Clock Family Reference Manual. This document can be downloaded from
Documentation)
Manual. In most designs, an external resistor voltage divider is recommended.
the allowed output format pin settings so that the maximum power dissipation for the TQFP devices is limited when they
are operated at 3.3 V. When there are four enabled LVPECL or CMOS outputs, the fifth output must be disabled. When
there are five enabled outputs, there can be no more than three outputs that are either LVPECL or CMOS.
Parameter
.
CKN
Symbol
CKN
SP
SP
CKN
CKN
CKO
V
J
V
V
J
OCM
GEN
SUBH
SPUR
PK
OD
SE
VCM
TRF
VIN
DC
PN
A
Phase Noise @ 100 kHz Offset
= –40 to 85 ºC)
(n > 1, n x F3 < 100 MHz)
f
f
f
IN
IN
IN
LVPECL output format
Preliminary Rev. 0.41
Whichever is smaller
Max spur @ n x F3
= f
= f
= f
50 kHz–80 MHz
12 kHz–20 MHz
Test Condition
100 kHz offset
OUT
100 Hz offset
10 kHz offset
OUT
OUT
1 MHz offset
1 kHz offset
2.5 V ±10%
3.3 V ±10%
100  load
1.8 V ±5%
line-to-line
LVPECL
20–80%
= 622.08 MHz,
= 622.08 MHz
= 622.08 MHz
www.silabs.com/timing
V
DD
Min
0.9
1.0
1.1
1.1
0.5
—
40
—
—
—
—
—
—
—
—
—
—
– 1.42
0
2
–110
–117
–130
0.05
Typ
300
300
–65
–95
–90
–98
—
—
—
—
—
—
—
—
—
—
V
(click on
DD
–100
–125
–110
Max
1.95
0.93
V
–87
420
410
–50
–85
–75
1.4
1.7
1.9
0.1
Si5368
60
11
—
– 1.25
DD
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs rms
fs rms
Unit
V
Vpp
dBc
dBc
dB
ns
ns
%
V
V
V
V
V
DD
5