SI5365-C-GQ Silicon Laboratories Inc, SI5365-C-GQ Datasheet - Page 12

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SI5365-C-GQ

Manufacturer Part Number
SI5365-C-GQ
Description
IC CLOCK MULTIPLIER PROG 100TQFP
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5365-C-GQ

Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI5365-C-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
SI5365-C-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Si5365
12
Pin #
GND
PAD
82
83
85
87
88
92
93
97
98
CKOUT1–
CKOUT1+
CKOUT5–
CKOUT5+
CKOUT2+
CKOUT2–
CKOUT4–
CKOUT4+
Pin Name
GND PAD GND
DBL34
I/O Signal Level
O
O
O
O
I
LVCMOS
Table 3. Si5365 Pin Descriptions (Continued)
Supply
MULTI
MULTI
MULTI
MULTI
Clock Output 1.
Differential output clock with a frequency specified by FRQSEL and
FRQTBL. Output signal format is selected by SFOUT pins. Output is dif-
ferential for LVPECL, LVDS, and CML compatible modes. For CMOS for-
mat, both output pins drive identical single-ended clock outputs.
Output 3 and 4 Disable.
Active high input. When active, entire CKOUT3 and CKOUT4 divider and
output buffer path is powered down. CKOUT3 and CKOUT4 outputs will
be in tristate mode during powerdown.
This pin has a weak pullup.
Clock Output 5.
Fifth high-speed clock output with a frequency specified by FRQSEL and
FRQTBL. Output signal format is selected by SFOUT pins. Output is dif-
ferential for LVPECL, LVDS, and CML compatible modes. For CMOS for-
mat, both output pins drive identical single-ended clock outputs.
Clock Output 2.
Differential output clock with a frequency specified by FRQSEL and
FRQTBL. Output signal format is selected by SFOUT pins. Output is dif-
ferential for LVPECL, LVDS, and CML compatible modes. For CMOS for-
mat, both output pins drive identical single-ended clock outputs.
Clock Output 4.
Differential output clock with a frequency specified by FRQSEL and
FRQTBL settings. Output signal format is selected by SFOUT pins. Out-
put is differential for LVPECL, LVDS, and CML compatible modes. For
CMOS format, both output pins drive identical single-ended clock outputs.
Ground Pad.
The ground pad must provide a low thermal and electrical impedance to a
ground plane.
Preliminary Rev. 0.4
Description

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