SI5365-C-GQ Silicon Laboratories Inc, SI5365-C-GQ Datasheet
SI5365-C-GQ
Specifications of SI5365-C-GQ
Available stocks
Related parts for SI5365-C-GQ
SI5365-C-GQ Summary of contents
Page 1
... VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or 2.5 V supply, the Si5365 is ideal for providing clock multiplication in high performance timing applications. Applications ...
Page 2
... Si5365 Table 1. Performance Specifications (V = 1.8 ±5% or 2.5 V ±10 – º Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F (CKIN1, CKIN2, CKIN3, CKIN4) Output Clock Frequency CK OF (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5) 3-Level Input Pins ...
Page 3
... Phase Noise @ 100 kHz — Offset Max spur @ — (n > < 100 MHz) Still Air — www.silabs.com/timing Symbol –0 DIG T JCT T STG Preliminary Rev. 0.4 Si5365 Typ Max Unit 0.6 TBD ps rms 0.6 TBD ps rms 0.05 0.1 dB TBD TBD dBc/Hz TBD TBD dBc/Hz TBD ...
Page 4
... Si5365 622 MHz In, 622 MHz Out BW=877 kHz -50 -70 -90 -110 -130 -150 -170 1000 10000 OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz OC-192, 50 kHz to 80 MHz Broadband, 800 MHz 4 100000 1000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot ...
Page 5
... CKOUT5 Disable DBL5 15 kΩ Reset RST Notes: 1. Assumes differential LVPECL termination (3 clock inputs. 2. Denotes tri-level input pins with states designated as L (ground Assumes manual input clock selection. Figure 2. Si5365 Typical Application Circuit C 10 Ferrite 1 µF Bead C 1–9 0.1 µF CKOUT1+ CKOUT1– ...
Page 6
... Si5365 1. Functional Description The Si5365 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, SDH STM-16/STM-64, Ethernet, and Fibre Channel, in which the application requires clock multiplication without jitter attenuation. The Si5365 accepts four clock inputs ranging from 19.44 to 707 MHz and generates five frequency-multiplied clock outputs ranging from 19 ...
Page 7
... NC 20, 23, 24, 25, 47, 48, 49, 52, 53, 72, 73, 74, 75 Si5365 GND PAD Table 3. Si5365 Pin Descriptions Description No Connect. These pins must be left unconnected for normal operation. Preliminary Rev. 0.4 Si5365 FRQSEL3 70 FRQSEL2 FRQSEL1 69 FRQSEL0 68 67 DIV34_1 66 DIV34_0 65 GND GND 64 63 VDD 62 VDD ...
Page 8
... Si5365 Table 3. Si5365 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 3 RST I LVCMOS 4 FRQTBL I 3-Level Supply DD DD 27, 32, 42, 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99, 100 7, 8, 14, GND GND Supply 16, 18, 19, 21, 26, 28, 31, 33, 36, 38, 41, 43, 46, 51, 54, 55, 56, 64 C1B ...
Page 9
... Table 3. Si5365 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 11 C3B O LVCMOS 12 ALRMOUT O LVCMOS 13 CS0_C3A I/O LVCMOS 57 CS1_C4A 22 AUTOSEL I 3-Level 29 CKIN4+ I MULTI 30 CKIN4– 34 CKIN2+ I MULTI 35 CKIN2– Description CKIN3 Invalid Indicator. This pin is an active high alarm output associated with CKIN3. ...
Page 10
... Si5365 Table 3. Si5365 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 37 DBL2_BY I 3-Level 39 CKIN3+ I MULTI 40 CKIN3– 44 CKIN1+ I MULTI 45 CKIN1– 50 DBL5 I 3-Level 56 FOS_CTL I 3-Level 58 C1A O LVCMOS 59 C2A O LVCMOS 10 Description CKOUT2 Disable/PLL Bypass Mode Control. Controls enable of CKOUT2 divider/output buffer path and PLL bypass mode ...
Page 11
... Table 3. Si5365 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 60 BWSEL0 I 3-Level 61 BWSEL1 66 DIV34_0 I 3-Level 67 DIV34_1 68 FRQSEL0 I 3-Level 69 FRQSEL1 70 FRQSEL2 71 FRQSEL3 77 CKOUT3+ O MULTI 78 CKOUT3– 80 SFOUT1 I 3-Level 95 SFOUT0 Description Bandwidth Select. These pins are three level inputs that select the DSPLL closed loop band- width according to the Any-Rate Precision Clock Family Reference Man- ual ...
Page 12
... Si5365 Table 3. Si5365 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 82 CKOUT1– O MULTI 83 CKOUT1+ 85 DBL34 I LVCMOS 87 CKOUT5– O MULTI 88 CKOUT5+ 92 CKOUT2+ O MULTI 93 CKOUT2– 97 CKOUT4– O MULTI 98 CKOUT4+ GND GND PAD GND Supply PAD 12 Description Clock Output 1. Differential output clock with a frequency specified by FRQSEL and FRQTBL ...
Page 13
... Ordering Guide Ordering Part Number Si5365-C-GQ 100-Pin TQFP Package ROHS6, Pb-Free Yes Preliminary Rev. 0.4 Si5365 Temperature Range – °C 13 ...
Page 14
... Si5365 4. Package Outline: 100-Pin TQFP Figure 3 illustrates the package details for the Si5365. Table 4 lists the values for the dimensions shown in the illustration. Figure 3. 100-Pin Thin Quad Flat Package (TQFP) Table 4. Dimension Min Nom A — A1 0.05 A2 0.95 1.00 b 0.17 0. ...
Page 15
... Recommended PCB Layout Figure 4. PCB Land Pattern Diagram Preliminary Rev. 0.4 Si5365 15 ...
Page 16
... Si5365 Table 5. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0 ...
Page 17
... Added “5. Recommended PCB Layout”. Revision 0.34 to Revision 0.4 Changed 1.8 V operating range to ±5%. Updated Table 1 on page 2. Updated Table 2 on page 3. Added page 4. Updated "1. Functional Description" on page 6. Clarified "2. Pin Descriptions: Si5365" on page 7 including the addition of FOS_CTL (pin 56). Preliminary Rev. 0.4 Si5365 17 ...
Page 18
... Si5365 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...