ICS9UMS9633BKILF IDT, Integrated Device Technology Inc, ICS9UMS9633BKILF Datasheet - Page 13

• Manufacturer Part Number: ICS9UMS9633BKILF
• Description: IC MOBILE PC CLK EMEBED 48VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PC Clockr

Specifications of ICS9UMS9633BKILF

• Input: Clock
• Output: Clock
• Frequency - Max: 167MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN
• Frequency-max: 167MHz
• Number Of Elements: 3
• Supply Current: 70mA
• Pll Input Freq (max): 15MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VFQFPN EP
• Output Frequency Range: 67 to 167MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9UMS9633BKILF

IDT
ICS9UMS9633BI
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE
Bit(s)
Bit(s)
Byte
Byte
TM
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
/ICS
TM
Ultra Mobile PC Clock for Industrial Temperature Range
Pin #
Pin #
0
1
-
-
-
-
-
-
-
-
PLL & Divider Enable Register
PLL SS Enable/Control Register
CPU Divider Enable
SRC Output Divider
DOT Output Divider
LCD Output Divider
PLL1 SS Enable
PLL3 SS Enable
PLL3 FS Select
PLL1 Enable
PLL2 Enable
PLL3 Enable
Enable
Enable
Enable
Name
Name
NOTE: This bit should be automatically set to ‘0’ if
NOTE: This bit should be automatically set to ‘0’ if
NOTE: This bit should be automatically set to ‘0’ if
NOTE: This bit should be automatically set to ‘0’ if
This bit controls whether PLL1 has spread enabled
This bit controls whether PLL3 has spread enabled
that the spread spectrum amount is set in bits 3-5.
This bit controls whether the CPU output divider is
This bit controls whether the SRC output divider is
This bit controls whether the DOT output divider is
This bit controls whether the LCD output divider is
These 3 bits select the frequency of PLL3 and the
This bit controls whether the PLL driving the DOT
down-spread. Note that PLL1 drives the CPU and
This bit controls whether the PLL driving the LCD
or not. Note that PLL3 drives the SSC clock, and
This bit controls whether the PLL driving the CPU
or not. Spread spectrum for PLL1 is set at -0.5%
SSC clock when Byte 1 Bit 6 (PLL3 Spread
and SRC clocks is enabled or not.
and clock is enabled or not.
Spectrum Enable) is set.
clock is enabled or not.
bit 7 is set to ‘0’.
bit 7 is set to ‘0’.
bit 5 is set to ‘0’.
bit 6 is set to ‘0’.
enabled or not.
enabled or not.
enabled or not.
enabled or not.
SRC clocks.
Description
Description
13
Reserved
Reserved
Reserved
Reserved
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
0 = Disabled
See Table 2: LCD Spread
Advance Information
0
0
Select Table
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1
1
1451—01/20/09
Default
Default
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0