ICS9EPRS475CGLFT IDT, Integrated Device Technology Inc, ICS9EPRS475CGLFT Datasheet - Page 15

• Manufacturer Part Number: ICS9EPRS475CGLFT
• Description: IC EMBEDDED PC MAIN CLK 56TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9EPRS475CGLFT

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT
1
1
2
outputs.
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
Absolute Maximum Rating
Electrical Characteristics - Input/Supply/Common Output Parameters
Guaranteed by design and characterization, not 100% tested in production.
Guaranteed by design and characterization, not 100% tested in production.
Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL
9EPRS475
System Clock for Embedded AMD
Input ESD protection HBM
®
3.3V Core Supply Voltage
3.3V Core Supply Voltage
Ambient Operating Temp
Low-level Output Voltage
Modulation Frequency
System Clock for Embedded AMD
Clock/Data Rise Time
Storage Temperature
Low Threshold Input-
Low Threshold Input-
Clock/Data Fall Time
Powerdown Current
Case Temperature
SMBCLK/SMBDAT
SMBCLK/SMBDAT
Input High Current
Input High Voltage
Input Low Current
Operating Current
Input Capacitance
Input Low Voltage
Current sinking at
Input Frequency
Clk Stabilization
Pin Inductance
SMBus Voltage
PARAMETER
PARAMETER
High Voltage
Low Voltage
Tdrive_PD
V
Trise_PD
Tfall_PD
OL
= 0.4 V
SYMBOL
Tambient
SYMBOL
I
ESD prot
VDDxxx
VDDxxx
PULLUPSMB
I
I
Tcase
V
V
V
DD3.3OP
DD3.3PD
T
V
T
T
C
C
DDSMB
OLSMB
L
C
Ts
V
V
I
I
IH_FS
RSMB
TM
IL_FS
STAB
FSMB
I
F
IL1
IL2
OUT
IH
pin
INX
IH
IL
IN
i
based Systems
TM
based Systems
V
3.3V VDD current, all outputs
IN
V
From VDD Power-Up or de-
assertion of PD to 1st clock
IN
= 0 V; Inputs with no pull-up
CPU output enable after
Output pin capacitance
Triangular Modulation
= 0 V; Inputs with pull-up
VDD = 3.3 V +/-5%
VDD = 3.3 V +/-5%
VDD = 3.3 V +/-5%
VDD = 3.3 V +/-5%
all diff pairs low/low
VDD = 3.3 V +/-5%
(Max VIL - 0.15) to
(Min VIH + 0.15) to
(Min VIH + 0.15)
(Max VIL - 0.15)
PD de-assertion
CONDITIONS*
PD rise time of
CONDITIONS
PD fall time of
X1 & X2 pins
Logic Inputs
V
resistors
@ I
resistors
IN
driven
= V
PULLUP
-
-
-
-
-
-
DD
15
3.135
2000
V
-200
V
MIN
MIN
-65
0.3
0.7
0.3
2.7
30
-5
-5
SS
SS
0
2
4
-
-
14.31818
TYP
TYP
3.3
3.3
6
GND + 3.9V
V
V
DD
DD
3.465
MAX
MAX
1000
0.35
150
115
115
300
300
0.8
1.8
5.5
0.4
70
12
33
5
7
5
6
5
5
5
+ 0.3
+ 0.3
UNITS
UNITS
MHz
kHz
mA
mA
nH
ms
mA
°C
°C
uA
uA
uA
pF
pF
pF
us
ns
ns
°
ns
ns
V
V
V
V
V
V
V
V
V
C
Notes
Notes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1615B—04/26/10