ICS9248BF-138T IDT, Integrated Device Technology Inc, ICS9248BF-138T Datasheet - Page 9

no-image

ICS9248BF-138T

Manufacturer Part Number
ICS9248BF-138T
Description
IC FREQ GENERATOR/BUFFER 48-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Frequency Generatorr
Datasheet

Specifications of ICS9248BF-138T

Input
Crystal
Output
Clock
Frequency - Max
200MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
9248BF-138T
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Notes:
1.
2.
3.
4.
5.
6.
0342C—08/26/03
through byte 5
The ICS clock generator is a slave/receiver, I
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
Dummy Command Code
Dummy Byte Count
Controller (Host)
Address
Start Bit
Stop Bit
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
D2
(H)
How to Write:
For more information, contact ICS for an I
The information in this section assumes familiarity with I
General I
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
2
C serial interface information
(H)
2
C component. It can read back the data stored in the latches for
9
2
C programming application note.
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Controller (Host)
Address
Start Bit
Stop Bit
D3
ACK
ACK
ACK
ACK
ACK
ACK
ACK
2
C programming.
(H)
How to Read:
ICS (Slave/Receiver)
ICS9248-138
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
(H)

Related parts for ICS9248BF-138T