ICS954309BKLFT IDT, Integrated Device Technology Inc, ICS954309BKLFT Datasheet - Page 3

• Manufacturer Part Number: ICS954309BKLFT
• Description: IC TIMING CTRL HUB P4 64-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS954309BKLFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-VFQFN, 64-VFQFPN
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 954309BKLFT

Pin Description (Continued)
1044A—02/20/07
NOTE: Only OE# pins have internal pull-up resistors. No other inputs have pull-up or pull-down resistors.
PIN #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
IREF
CPUCLKC1
CPUCLKT1
VDDCPU
GNDCPU
CPUCLKC0
CPUCLKT0
CPU_STOP#
SMBCLK
SMBDAT
VDDREF
X2
X1
GNDREF
REF
VDDPCI
PCICLK3
PCICLK2
PCICLK1
PCICLK0
ITP_EN/PCICLK_F0
VDDPCI
GNDPCI
VTT_PWRGD#/PD
FS_C/TEST_SEL
USB_48MHZ/FS_A
GNDPCI
VDD48
DOTT_96MHZ
DOTC_96MHZ
FS_B/TEST_MODE
OE1#
Integrated
Circuit
Systems, Inc.
PIN NAME
PIN TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
I/O
I/O
IN
IN
IN
IN
IN
IN
IN
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to
establish the appropriate current. 475 ohms is the standard value.
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Ground pin for the CPU outputs
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Stops all CPUCLK, except those set to be free running clocks
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin for the REF outputs.
14.318 MHz reference clock.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
Power supply for PCI clocks, nominal 3.3V
Ground pin for the PCI outputs
Vtt_PwrGd# is an active low input used to determine when latched inputs are
ready to be sampled. PD is an asynchronous active high input pin used to put the
device into a low power state. The internal clocks, PLLs and the crystal oscillator
are stopped.
see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
Frequency select latch input pin / Fixed 48MHz USB clock output. 3.3V.
Ground pin for the PCI outputs
Power pin for the 48MHz output.3.3V
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to
select between Hi-Z and REF/N divider mode while in test mode. Refer to Test
Clarification Table.
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
1 = CPU_ITP pair
0 = SRC pair
3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs,
3.3V tolerant input for CPU frequency selection. Refer to input electrical
3
DESCRIPTION
ICS954309