ICS954206BFT IDT, Integrated Device Technology Inc, ICS954206BFT Datasheet - Page 14

• Manufacturer Part Number: ICS954206BFT
• Description: IC TIMING CTRL HUB P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS954206BFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 954206BFT

0940—06/23/05
I
I
I
I
2
2
2
2
C Table: Byte Count Register
C Table: Watchdog Timer Register
C Table: VCO Control Select Bit & WD Timer Control Register
C Table: VCO Frequency Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 5
Byte 10
Byte 11
Byte 8
Byte 9
Integrated
Circuit
Systems, Inc.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
LCDCLK/PCIEX0 SEL
WD Safe Freq Source
LCDCLK/PCIEX0
WD Hard Status
WD Soft Status
REQ_SEL
WDH_EN
WDS_EN
WD SFC
WDTCtrl
M/N_EN
WD SFB
WD SFA
N Div 9
N Div8
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Name
Name
Name
Name
WD2
WD1
WD0
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Byte Count Programming
M Divider Programming
WD Hard Alarm Status
SELPCIEX0/LCDCLK#
Watch Dog Time base
Watchdog Hard Alarm
PLLM/N Programming
WD Safe Freq Source
WD Soft Alarm Status
Watch Dog Safe Freq
Watchdog Soft Alarm
N Divider Prog bit 8
N Divider Prog bit 9
Programming bits
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
Driven in PD
Function
Function
Function
REQ_SEL
Function
Control
Control
Control
Control
Control
Enable
Enable
Enable
b(7:0)
bits
14
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
the watchdog timer waits before it goes to
These bits represent X*290ms (or 1.16S)
Divier in Byte 11 and 12 will configure the
Writing to these bit will configure the safe
Writing to this register will configure how
alarm mode. Default is 7 X 290ms = 2s.
many bytes will be read back, default is
The decimal representation of M and N
VCO frequency. Default at power up =
Inputs/Byte6[2:0]
Frequency = 14.318 x [NDiv(9:0)+8] /
290ms Base
latch-in or Byte 0 Rom table. VCO
LCDCLK
Disable
Disable
Disable
PCIEX5
Normal
Normal
frequency as Byte0 bit (4:0).
Driven
Latch
0
0
0
0
Advance Information
0F = 15 bytes.
[MDiv(5:0)+2]
1160ms Base
B10b(2:0)
PCIEX0
PEREQ
Enable
Enable
Enable
Alarm
Alarm
Hi-Z
ICS954206B
1
1
1
1
PWD
PWD
PWD
PWD
latch
latch
0
0
0
0
1
1
1
1
0
0
X
X
0
1
1
1
0
0
0
0
0
X
X
X
X
X
X
X
X
0