ICS9LPRS365BKLFT IDT, Integrated Device Technology Inc, ICS9LPRS365BKLFT Datasheet - Page 8

• Manufacturer Part Number: ICS9LPRS365BKLFT
• Description: IC CLK SYNTHESIZR CK505 64VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9LPRS365BKLFT

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: *
• Frequency-max: *
• Number Of Elements: 3
• Supply Current: 250mA
• Pll Input Freq (max): 14.318MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: VFQFPN EP
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 9LPRS365BKLFT

MLF Pin Description (Continued)
1218—09/01/10
PIN #
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
USB_48MHz/FSLA
GND48
VDD96_IO
DOTT_96/SRCT0
DOTC_96/SRCC0
GND
VDD
27MHz_NonSS/SRCT1/SE1
27MHz_SS/SRCC1/SE2
GND
VDDPLL3_IO
SRCT2/SATAT
SRCC2/SATAC
GNDSRC
SRCT3/CR#_C
SRCC3/CR#_D
PIN NAME
TYPE
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
I/O
I/O
I/O
DESCRIPTION
input electrical characteristics for Vil_FS and Vih_FS values.
Ground pin for the 48MHz outputs.
True clock of SRC or DOT96. The power-up default function depends on 27_Select, 1= SRC0,
0=DOT96
Complement clock of SRC or DOT96. The power-up default function depends on 27_Select,1=
SRC0, 0=DOT96
Ground pin for the DOT96 clocks.
Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
True clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determines the
power-up default, 1=27MHz non-spread SE clock, 0 = LCD_SST 100MHz differential clock. See
table 2 for more information.
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select
determines the power-up default, 1=27MHz spread SE clock, 0 = LCD_SSC 100MHz differential
clock. See table 2 for more information.
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
1.05V to 3.3V from external power supply
True clock of differential SRC/SATA clock pair.
Complement clock of differential SRC/SATA clock pair.
Ground pin for SRC clocks.
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request
Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the
SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC
pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1
or SRC4 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request
Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the
SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC
pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to
1.05V to 3.3V from external power supply
Byte 5, bit 2
Byte 5, bit 0
8
ICS9LPRS365
Datasheet