ICS9FGP202AKLF IDT, Integrated Device Technology Inc, ICS9FGP202AKLF Datasheet - Page 15

• Manufacturer Part Number: ICS9FGP202AKLF
• Description: IC FREQ TIMING GENERATOR 40VFQFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr
• Series: -r

Specifications of ICS9FGP202AKLF

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 400MHz
• Number Of Elements: 3
• Supply Current: 200mA
• Pll Input Freq (min): 25MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: VFQFPN EP
• Output Frequency Range: 25 to 400MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 40
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 9FGP202AKLF

1339C—09/14/09
SMBus Table: CPU PLL VCO Frequency Control Register
SMBus Table: CPU PLL VCO Frequency Control Register
SMBus Table: CPU PLL Spread Spectrum Control Register
SMBus Table: CPU PLL Spread Spectrum Control Register
SMBus Table: DOT PLL VCO Frequency Control Register
SMBus Table: DOT PLL VCO Frequency Control Register
Byte 11
Byte 12
Byte 13
Byte 14
Byte 15
Byte 16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Integrated
Circuit
Systems, Inc.
Pin #
Pin #
Pin #
Pin #
Pin #
Pin #
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N Div 9
N Div8
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
SSP14
SSP13
SSP12
SSP11
SSP10
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Name
Name
Name
Name
Name
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
SSP9
SSP8
Spread Spectrum Programming
Spread Spectrum Programming
N Divider Programming b(7:0)
N Divider Programming b(7:0)
M Divider Programming bits
M Divider Programming bits
N Divider Prog bit 8
N Divider Prog bit 8
N Divider Prog bit 9
N Divider Prog bit 9
Control Function
Control Function
Control Function
Control Function
Control Function
Control Function
Reserved
b(14:8)
b(7:0)
15
Type
Type
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
up = latch-in or Byte 0 Rom table. VCO
up = latch-in or Byte 0 Rom table. VCO
These Spread Spectrum bits in Byte 13
These Spread Spectrum bits in Byte 13
The decimal representation of M and N
The decimal representation of M and N
The decimal representation of M and N
The decimal representation of M and N
Divier in Byte 11 and 12 will configure
Divier in Byte 11 and 12 will configure
pecentage. It is recommended to use
pecentage. It is recommended to use
the VCO frequency. Default at power
Frequency = 14.318 x [NDiv(9:0)+8] /
the VCO frequency. Default at power
Frequency = 14.318 x [NDiv(9:0)+8] /
Divier in Byte 17 and 18 will configure
the VCO frequency. Default at power
Divier in Byte 17 and 18 will configure
the VCO frequency. Default at power
Frequency = 14.318 x [NDiv(9:0)+8] /
Frequency = 14.318 x [NDiv(9:0)+8] /
and 14 will program the spread
ICS Spread % table for spread
and 14 will program the spread
ICS Spread % table for spread
up = Byte 0 Rom table. VCO
up = Byte 0 Rom table. VCO
0
0
0
0
0
0
[MDiv(5:0)+2]
[MDiv(5:0)+2]
programming.
programming.
[MDiv(5:0)+2]
[MDiv(5:0)+2]
ICS9FGP202A
1
1
1
1
1
1
PWD
PWD
PWD
PWD
PWD
PWD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0