ICS9161A-01CW16LFT IDT, Integrated Device Technology Inc, ICS9161A-01CW16LFT Datasheet
ICS9161A-01CW16LFT
Specifications of ICS9161A-01CW16LFT
Related parts for ICS9161A-01CW16LFT
ICS9161A-01CW16LFT Summary of contents
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... The flexibility of the device allows it to generate non-standard graphics clocks. The ICS9161A is also ideal in disk drives. It can generate zone clocks for constant density recording schemes. The low profile, 16-pin SOIC or PDIP package and low jitter outputs are especially attractive in board space critical disk drives ...
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... Pin Descriptions 0210I—03/21/05 Pin Configuration 16-Pin 300- mil SOIC or PDIP ICS9161A ...
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... The ICS9161A places the three video clock registers and the memory clock register in a known state upon power- up. The registers are initialized based on the state of the INIT1 and INIT0 pins at application of power to the device. The INIT pins must ramp up with VDD if a logical 1 on either pin is required ...
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... Control Register Definitions The control register allows the user to adjust various internal options. The register is defined as follows 0210I—03/21/ ICS9161A ...
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... The pins SEL0 and SEL1 perform the dual functions of select-ing registers and serial programming. In serial programming mode, SEL0 acts as a clock pin while SEL1 acts as the data pin. The ICS9161A-01 may not be serially programmed when in power-down mode. In order to program a particular register, an unlocking sequence must occur ...
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... DD Unlike the ICD2061A, the ICS9161A’s VCO does not F =Input Reference REF require tuning to place it in certain ranges. The ICS9161A’s Frequency VCO will operate from 50 MHz to 120 MHz without M=Reference divide 3 to 129 adjusting the VCO gain. However, to maintain compatibility, the I bits are programmed as in the ICD2061A ...
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... Power Management Issues Power-down mode 1 The ICS9161A contains a mechanism to reduce the quiescent power when stand-by operation is desired. Power-down mode 1 is invoked by polling PD# low and having the proper CNTL register bit set to zero. In this mode, VCOs are shut down, the VCLK output is forced high, and the MCLK output is set to a user-defined low frequency value to refresh dynamic RAM ...
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... Electrical Characteristics at 5.0V = +5V ± 5%, 0°C ≤ AMBIENT Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 0210I—03/21/05 ) ..............0°C to 70°C OPER ) ............+260°C SOL ≤ +70° ICS9161A µ A µ A µ µ ...
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... For reference frequencies other than 14.81818 MHz, the pre-loaded ROM frequencies will shift proportionally. 3. Duty cycle is measured at CMOS threshold levels volts the interval is too short, see the time-out interval section in the control register definition. 0210I—03/21/05 (continued • ICS9161A =2.5 volts. TH ...
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... Rise and Fall Times Tristated Timing 10 ICS9161A ...
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... MCLK and Active VCLK Register Programming Timing 0210I—03/21/05 Selection Timing 11 ICS9161A ...
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... Soft Power-Down Timing (Mode 2) 0210I—03/21/05 Serial Programming Timing 12 ICS9161A ...
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... RC termination should be used on all over 50MHz outputs. 3) Optional crystal load capacitors are recommended. Capacitor Values: C1 Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01µF ceramic Connections to VDD: 0210I—03/21/05 13 ICS9161A ...
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... Lead Count & Package Width Lead Count= digits W=.3” SOIC or .6” DIP; None=Standard Width Package Type N=DIP (Plastic) Pattern Number ( digit number for parts with ROM code patterns, if applicable) Device Type (consists digit numbers) Prefix ICS, AV=Standard Device 14 ICS9161A ...
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... Annealed Lead Free (Optional) Lead Count & Package Width Lead Count= digits W=.3” SOIC or .6” DIP; None=Standard Width Package Type M=SOIC Pattern Number ( digit number for parts with ROM code patterns, if applicable) Device Type (consists digit numbers) Prefix ICS, AV=Standard Device 15 ICS9161A ...