ICS95V842AFLF IDT, Integrated Device Technology Inc, ICS95V842AFLF Datasheet - Page 2

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ICS95V842AFLF

Manufacturer Part Number
ICS95V842AFLF
Description
IC DVR DDR PLL 16-QSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Driverr
Datasheet

Specifications of ICS95V842AFLF

Input
Clock
Output
Clock
Frequency - Max
333MHz
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-QSOP
Frequency-max
333MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
95V842AFLF
Pin Descriptions
ICS95V842
0830B—11/24/08
PIN #
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
FB_OUTC
FB_OUTT
PIN NAME
CLK_INC
CLK_INT
VDD2.5
DDRC0
FB_INC
VDD2.5
DDRC1
DDRT0
FB_INT
DDRT1
AGND
AVDD
GND
GND
PIN TYPE
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
"True" reference clock input.
"Complementary" reference clock input.
3.3V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
Complement single-ended feedback output, dedicated external
feedback. It switches at the same frequency as other DDR outputs,
This output must be connect to FB_INC.
True single-ended feedback output, dedicated external feedback. It
switches at the same frequency as other DDR outputs, This output
must be connect to FB_INT.
True single-ended feedback input, provides feedback signal to internal
PLL for synchronization with CLK_INT to eliminate phase error.
Complement single-ended feedback input, provides feedback signal to
internal PLL for synchronization with CLK_INT to eliminate phase
error.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
2
DESCRIPTION

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