ICS97ULP877BKLFT IDT, Integrated Device Technology Inc, ICS97ULP877BKLFT Datasheet
ICS97ULP877BKLFT
Specifications of ICS97ULP877BKLFT
Available stocks
Related parts for ICS97ULP877BKLFT
ICS97ULP877BKLFT Summary of contents
Page 1
Integrated Circuit Systems, Inc. 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: • DDR2 Memory Modules / Zero Delay Board Fan Out • Provides complete DDR DIMM logic solution with ICSSSTU32864/SSTUF32864/SSTUF32866/ SSTUA32864/SSTUA32866/SSTUA32S868/ SSTUA32S865/SSTUA32S869 Product Description/Features: • Low skew, low jitter ...
Page 2
ICS97ULP877B Pin Descriptions ...
Page 3
Function Table ...
Page 4
ICS97ULP877B Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD -0.5V to 2.5V Logic Inputs . . . . . . . . . . . . . . . . . ...
Page 5
Recommended Operating Condition (see note1 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER SYMBOL Supply Voltage V DDQ Low level input voltage V High level input voltage V DC ...
Page 6
ICS97ULP877B Timing Requirements 70°C Supply Voltage AVDD, VDDQ = 1 0.1V (unless otherwise stated) A PARAMETER Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization NOTE: The PLL must be ...
Page 7
Switching Characteristics 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER SYMBOL Output enable time Output disable time Period jitter t Half-period jitter Input slew rate Output clock slew ...
Page 8
ICS97ULP877B VDD/2 ICS97ULP877B -VDD FB_OUTC FB_OUTT X 0981C—04/05/05 Parameter Measurement Information V DD ICS97ULP877B GND Figure 1. IBIS Model Output Load GND R = 10Ω 0Ω Z ...
Page 9
CLK_INC CLK_INT FB_INC FB_INT FB_OUTC FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 0981C—04/05/05 Parameter Measurement Information ...
Page 10
ICS97ULP877B Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 0981C—04/05/05 Parameter Measurement Information t jit(hper_n) t jit(hper_n+ jit(hper) jit(hper_n) 2xf O Figure 7. Half-Period Jitter 80% t ...
Page 11
CK CK FBIN FBIN t ( )dyn Figure 10. Time delay between OE and Clock Output (Y, Y) 0981C—04/05/ SSC OFF SSC )dyn Figure 9. Dynamic Phase Offset ...
Page 12
ICS97ULP877B - Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one GND via (farthest from PLL). - ...
Page 13
A1 D TOP VIEW E ALL DIMENSIONS IN MILLIMETERS Min/Max 7.00 Bsc 4.50 Bsc 0.86/1.00 0.65 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC ...
Page 14
ICS97ULP877B Index Area Top View D THERMALLY ENHANCED, VERY THIN, FINE PITCH BASIC D2 M IN. / MAX IN. / MAX. L MIN. / MAX. Source ...