ICS952703BFT IDT, Integrated Device Technology Inc, ICS952703BFT Datasheet - Page 15

• Manufacturer Part Number: ICS952703BFT
• Description: IC TIMING CTRL HUB K7 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS952703BFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 217.9MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Frequency-max: 217.9MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 952703BFT

PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state
of the stopped CPU signals is CPUT=Low and CPUC=High. There is to be no change to the output drive current values. The CPUT
will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# Functionality
0813B—05/17/05
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next
high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
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Assertion of CPU_STOP# Waveforms
Assertion of PCI_STOP# Waveforms
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Preliminary Product Preview
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C configuration to be stoppable via assertion
ICS952703