IDTCV115-4PVG8 IDT, Integrated Device Technology Inc, IDTCV115-4PVG8 Datasheet - Page 17
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IDTCV115-4PVG8
Manufacturer Part Number
IDTCV115-4PVG8
Description
IC FLEXPC CLK PROGR P4 56-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
FlexPC™r
Type
PC Clockr
Datasheet
1.IDTCV115-4PVG8.pdf
(19 pages)
Specifications of IDTCV115-4PVG8
Input
Crystal
Output
Clock
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Frequency-max
400MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
CV115-4PVG8
PD#, POWER DOWN
before turning off the VCO. In PD# de-assertion all clocks will start without glitches.
PD# ASSERTION
low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive
mode is set to ‘tri-state’, the differential pair will be stopped in tri-state mode, undriven. When the drive mode but corresponding to the CPU or SRC clock of
interest is set to ‘0’ the true clock will be driven high at 2 x I
clocks will be tristated.
IDTCV115-4
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low
PD# should be sampled low by two consecutive CPU# rising edges before stopping clocks. All single-ended clocks will be held low on their next high to
P
WRDWN
1
0
#
CPU# 133MHz
SRC# 100MHz
I
REF 14.31818
REF
CPU 133MHz
SRC 100MHz
USB 48MHz
Normal
PCI 33MHz
* 2 or float
CPU
P
WRDWN#
Normal
CPU#
Float
I
REF
Normal
* 2 or float
SRC
REF
and the complementary clock will be tristated. If the control register is programmed to ‘1’ both
Normal
SRC#
Float
17
PCIF/PCI
33MHz
Low
48MHz
USB
Low
COMMERCIAL TEMPERATURE RANGE
I
REF
DOT96
Normal
* 2 or float
DOT96#
Normal
Float
14.318MHz
REF
Low