AD9548BCPZ Analog Devices Inc, AD9548BCPZ Datasheet - Page 73

• Manufacturer Part Number: AD9548BCPZ
• Description: IC CLOCK GEN/SYNCHRONIZR 88LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9548BCPZ

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 88-LFCSP
• Frequency-max: *
• Clock Ic Type: Clock Synthesizer
• Ic Interface Type: Serial
• Frequency: 1GHz
• No. Of Outputs: 4
• No. Of Multipliers / Dividers: 4
• Supply Current: 190mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register 0209 to Register 0210—IRQ Mask
The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (Address 0D02 to Address 0D09).
When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask
bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts.
Table 49. IRQ Mask for SYSCLK
Address
0209
Table 50. IRQ Mask for Distribution Sync, Watchdog Timer, and EEPROM
Address
020A
Table 51. IRQ Mask for the Digital PLL
Address
020B
Table 52. IRQ Mask for History Update, Frequency Limit, and Phase Slew Limit
Address
020C
[7:6]
[5]
[4]
[3:2]
[1]
[0]
[7:4]
[3]
[2]
[1]
[0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7:5]
[4]
[3]
[2]
[1]
[0]
Bits
Bits
Bits
Bits
Bit Name
Unused
SYSCLK unlocked
SYSCLK locked
Unused
SYSCLK Cal complete
SYSCLK Cal started
Bit Name
Unused
Distribution sync
Watchdog timer
EEPROM fault
EEPROM complete
Bit Name
Switching
Closed
Freerun
Holdover
Freq unlocked
Freq locked
Phase unlocked
Phase locked
Bit Name
Unused
History updated
Frequency unclamped
Frequency clamped
Phase slew unlimited
Phase slew limited
Description
Enables IRQ for indicating a SYSCLK PLL state transition from locked to unlocked
Enables IRQ for indicating a SYSCLK PLL state transition from unlocked to locked
Enables IRQ for indicating that SYSCLK calibration has completed
Enables IRQ for indicating that SYSCLK calibration has begun
Description
Enables IRQ for indicating that the DPLL is switching to a new reference
Enables IRQ for indicating that the DPLL has entered closed-loop operation
Enables IRQ for indicating that the DPLL has entered free-run mode
Enables IRQ for indicating that the DPLL has entered holdover mode
Enables IRQ for indicating that the DPLL lost frequency lock
Enables IRQ for indicating that the DPLL has acquired frequency lock
Enables IRQ for indicating that the DPLL lost phase lock
Enables IRQ for indicating that the DPLL has acquired phase lock
Description
Enables IRQ for indicating a distribution sync event
Enables IRQ for indicating expiration of the watchdog timer
Enables IRQ for indicating a fault during an EEPROM load or save operation
Enables IRQ for indicating successful completion of an EEPROM load or save
operation
Description
Enables IRQ for indicating the occurrence of a tuning word history update
Enables IRQ for indicating a state transition frequency limiter from clamped to
unclamped
Enables IRQ for indicating a state transition of the frequency limiter from
unclamped to clamped
Enables IRQ for indicating a state transition of the phase slew limiter from slew
limiting to not slew limiting
Enables IRQ for indicating a state transition of the phase slew limiter from not slew
limiting to slew limiting
Rev. A | Page 73 of 112
AD9548