ICS98ULPA877AKILF IDT, Integrated Device Technology Inc, ICS98ULPA877AKILF Datasheet
ICS98ULPA877AKILF
Specifications of ICS98ULPA877AKILF
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ICS98ULPA877AKILF Summary of contents
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Integrated Circuit Systems, Inc. 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: • DDR2 Memory Modules / Zero Delay Board Fan Out • Provides complete DDR2 DIMM logic solution Product Description/Features: • Low skew, low jitter PLL clock driver • ...
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ICS98ULPA877A Pin Descriptions ...
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ICS98ULPA877A is available in Commercial Temperature Range (0°C to 70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering Information for details Function Table ...
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ICS98ULPA877A Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD -0.5V to 2.5V Logic Inputs . . . . . . . . . . . . . . . . . ...
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Recommended Operating Condition (see note1) Commercial 0°C - 70°C; Industrial -40°C - +85°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL Supply Voltage V DDQ Low level input voltage V ...
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ICS98ULPA877A Timing Requirements Commercial 0°C - 70°C; Industrial -40°C - +85°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL Max clock frequency Application Frequency Range Input clock duty cycle CLK ...
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Switching Characteristics Commercial 0°C - 70°C; Industrial -40°C - +85°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL Output enable time Output disable time t Period jitter t Half-period ...
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ICS98ULPA877A ICS98ULPA877A 2.97" 2.97" Yx, FB_OUTC Yx, FB_OUTT 1177F—12/10/09 Parameter Measurement Information V DD ICS98ULPA877A V (CLK) V GND Figure 1: IBIS Model Output ...
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CLK_INC CLK_INT CLK_INC CLK_INT Yx# Yx Yx, FB_OUTC Yx, FB_OUTT Yx, FB_OUTC Yx, FB_OUTT Yx, FB_OUTC Yx, FB_OUTT 1177F—12/10/09 Parameter Measurement Information Figure 4: Static Phase Offset t ...
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ICS98ULPA877A Yx, FB_OUTC Yx, FB_OUTT 20% Clock Inputs and outputs 1177F—12/10/09 Parameter Measurement Information t JIT(HPER_n JIT(HPER) JIT(HPER_n) 2xfo Figure 7: Half-Period Jitter 80% t SLR Figure 8: Input and Output Slew Rates ...
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CLK# CLK FBIN# FBIN SSC OFF SSC ON t( )dyn Figure 10: Time Delay Between OE and Clock Output (Y, Y#) 1177F—12/10/ )dyn Figure 9: Dynamic Phase Offset 50% V DDQ ...
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ICS98ULPA877A VIA 1 CARD V DDQ GND VIA CARD *Place the 2200pF capacitors close to the PLL. *Use wide traces for PLL Analog power and GND. Connect PLL and caps to AGND trace and connect trace to one GND via ...
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A1 D TOP VIEW E ALL DIMENSIONS IN MILLIMETERS Min/Max 7.00 Bsc 4.50 Bsc 0.86/1.00 0.65 Bsc Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEDEC ...
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ICS98ULPA877A Index Area Top View D THERMALLY ENHANCED, VERY THIN, FINE PITCH BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. Source Reference: MLF2™ ...