ICS9FG104DGLF IDT, Integrated Device Technology Inc, ICS9FG104DGLF Datasheet - Page 10

• Manufacturer Part Number: ICS9FG104DGLF
• Description: IC FREQ TIMING GENERATOR 28TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS9FG104DGLF

• Input: Clock, Crystal
• Output: Differential
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: 400MHz
• Number Of Elements: 1
• Supply Current: 150mA
• Pll Input Freq (min): 12.886MHz
• Pll Input Freq (max): 27.5MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Output Frequency Range: 100 to 400MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1977-5; 9FG104DGLF; ICS9FG104DGLF

IDT
SMBus Table: Reserved Register
SMBus Table: Reserved Register
SMBus Table: M/N Programming Enable
SMBus Table: PLL Frequency Control Register
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
®
Byte 10
Byte 7
Byte 8
Byte 9
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Pin #
Pin #
Pin #
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
REFOUT_En
M/N_Enable
PLL M Div5
PLL M Div4
PLL M Div3
PLL M Div2
PLL M Div1
PLL M Div0
PLL N Div8
PLL N Div9
Name
Name
Name
Name
M Divider Programming
N Divider Prog bit 8
N Divider Prog bit 9
Control Function
Control Function
Control Function
Control Function
M/N Prog. Enable
REFOUT Enable
bit (5:0)
10
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
and N Divider in Byte 11 and 12 will
Byte 0 Rom table. VCO Frequency
configure the PLL VCO frequency.
The decimal representation of M
Default at power up = latch-in or
Disable
Disable
= fXTAL x [NDiv(9:0)+8] /
0
0
0
0
[MDiv(5:0)+2]
Enable
Enable
1
1
1
1
Default
Default
Default
Default
1541C—12/16/10
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0