PIC24FV16KA301-I/P Microchip Technology, PIC24FV16KA301-I/P Datasheet - Page 3

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PIC24FV16KA301-I/P

Manufacturer Part Number
PIC24FV16KA301-I/P
Description
MCU 16KB FLASH 2KB RAM 20-PDIP
Manufacturer
Microchip Technology
Datasheet

Specifications of PIC24FV16KA301-I/P

Controller Family/series
PIC24F
Core Size
16bit
No. Of I/o's
17
Program Memory Size
16KB
Eeprom Memory Size
512Byte
Ram Memory Size
2KB
Cpu Speed
32MHz
Oscillator Type
External, Internal
Rohs Compliant
Yes
Processor Series
PIC24FV
Core
PIC
Data Bus Width
16 bit
Program Memory Type
Flash
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-20
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Power Management Modes:
• Run – CPU, Flash, SRAM and Peripherals On
• Doze – CPU Clock Runs Slower than Peripherals
• Idle – CPU Off, Flash, SRAM and Peripherals On
• Sleep – CPU, Flash and Peripherals Off and SRAM on
• Deep Sleep – CPU, Flash, SRAM and Most Peripherals
• Low-Power Consumption:
High-Performance CPU:
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator with 4x PLL Option and
• 17-Bit by 17-Bit Single-Cycle Hardware Multiplier
• 32-Bit by 16-Bit Hardware Divider 16-Bit x 16-Bit
• C Compiler Optimized Instruction Set Architecture
Peripheral Features:
• Hardware Real-Time Clock and Calendar (RTCC):
• Programmable 32-bit Cyclic Redundancy Check
• Multiple Serial Communication modules:
• Five 16-Bit Timers/Counters with Programmable
• Three 16-Bit Capture Inputs with Dedicated Timers
• Three 16-Bit Compare/PWM Output with Dedicated
• Configurable Open-Drain Outputs on Digital I/O Pins
• Up to Three External Interrupt Sources
 2011 Microchip Technology Inc.
Off; Multiple Autonomous Wake-up Sources
- Run mode currents down to 8 μA, typical
- Idle mode currents down to 2.2 μA, typical
- Deep Sleep mode currents down to 20 nA, typical
- Real-Time Clock/Calendar currents down to
- Watchdog Timer 500 nA, 1.8V typical
Multiple Divide Options
Working Register Array
- Provides clock, calendar and alarm functions
- Can run in Deep Sleep mode
- Can use 50/60 Hz power line input as clock source
(CRC)
- Two 3-/4-wire SPI modules
- Two I
- Two UART modules supporting RS-485, RS-232,
Prescaler:
- Can be paired as 32-bit timers/counters
Timers
700 nA, 32 kHz, 1.8V
LIN/J2602, IrDA
2
C™ modules with multi-master/slave support
20/28/44/48-Pin, General Purpose, 16-Bit Flash
®
Microcontrollers with XLP Technology
PIC24FV32KA304 FAMILY
Analog Features:
• 12-Bit, up to 16-Channel Analog-to-Digital Converter:
• Dual Rail-to-Rail Analog Comparators with
• On-Chip Voltage Reference
• Internal Temperature Sensor
• Charge Time Measurement Unit (CTMU):
Special Microcontroller Features:
• Wide Operating Voltage Range:
• Low Power Wake-up Sources and Supervisors:
• System Frequency Range Declaration bits:
• Standard Watchdog Timer (WDT) with On-Chip,
• Programmable High/Low-Voltage Detect (HLVD)
• Standard Brown-out Reset (BOR) with 3 Programmable
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
• Flash Program Memory:
• Data EEPROM:
• Fail-Safe Clock Monitor
• Programmable Reference Clock Output
• Self-Programmable under Software Control
• In-Circuit Serial Programming™ (ICSP™) and
- 100 ksps conversion rate
- Conversion available during Sleep and Idle
- Auto-sampling timer-based option for Sleep and
- Wake on auto-compare option
Programmable Input/Output Configuration
- Used for capacitance sensing, 16 channels
- Time measurement, down to 200 ps resolution
- Delay/pulse generation, down to 1 ns resolution
- 1.8V to 3.6V (PIC24F devices)
- 2.0V to 5.5V (PIC24FV devices)
- Ultra-Low Power Wake-up (ULPWU) for
- Low-Power Watchdog Timer (DSWDT) for
- Extreme Low-Power Brown-out Reset (DSBOR)
- Declaring the frequency range optimizes the
Low-Power RC Oscillator for Reliable Operation
Trip Points that can be Disabled in Sleep
- Erase/write cycles: 10,000 minimum
- 40 years’ data retention minimum
- Erase/write cycles: 100,000 minimum
- 40 years’ data retention minimum
In-Circuit Debug (ICD) via 2 Pins
Idle modes
Sleep/Deep Sleep
Deep Sleep
for Deep Sleep, LPBOR for all other modes
current consumption.
DS39995B-page 3

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