PIC24FV16KA301-I/P Microchip Technology, PIC24FV16KA301-I/P Datasheet - Page 124
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PIC24FV16KA301-I/P
Manufacturer Part Number
PIC24FV16KA301-I/P
Description
MCU 16KB FLASH 2KB RAM 20-PDIP
Manufacturer
Microchip Technology
Datasheet
1.PIC24FV16KA301-IP.pdf
(320 pages)
Specifications of PIC24FV16KA301-I/P
Controller Family/series
PIC24F
Core Size
16bit
No. Of I/o's
17
Program Memory Size
16KB
Eeprom Memory Size
512Byte
Ram Memory Size
2KB
Cpu Speed
32MHz
Oscillator Type
External, Internal
Rohs Compliant
Yes
Processor Series
PIC24FV
Core
PIC
Data Bus Width
16 bit
Program Memory Type
Flash
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-20
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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- Download datasheet (3Mb)
PIC24FV32KA304 FAMILY
The following code sequence for a clock switch is
recommended:
1.
2.
3.
4.
5.
6.
7.
8.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is shown in
EXAMPLE 9-1:
DS39995B-page 124
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV
MOV
MOV
MOV.b
MOV.b
;Set new oscillator selection
MOV.b
;OSCCONL (low byte) unlock sequence
MOV
MOV
MOV
MOV.b
MOV.b
;Start oscillator switch operation
BSET
Disable interrupts during the OSCCON register
unlock and write sequence.
Execute the unlock sequence for the OSCCON
high
OSCCON<15:8> in two back-to-back instructions.
Write new oscillator source to the NOSCx bits in
the instruction immediately following the unlock
sequence.
Execute the unlock sequence for the OSCCON
low
OSCCON<7:0> in two back-to-back instructions.
Set the OSWEN bit in the instruction immediately
following the unlock sequence.
Continue to execute code that is not
clock-sensitive (optional).
Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then check
the LOCK bit to determine the cause of failure.
byte
byte
#OSCCONH, w1
#0x78, w2
#0x9A, w3
w2, [w1]
w3, [w1]
WREG, OSCCONH
#OSCCONL, w1
#0x46, w2
#0x57, w3
w2, [w1]
w3, [w1]
OSCCON,#0
by
by
writing
writing
BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
46h
78h
and
and
Example
9Ah
57h
9-1.
to
to
9.5
In addition to the CLKO output (F
certain oscillator modes, the device clock in the
PIC24FV32KA304
configured to provide a reference clock output signal to
a port pin. This feature is available in all oscillator
configurations and allows the user to select a greater
range of clock submultiples to drive external devices in
the application.
This reference clock output is controlled by the
REFOCON register
bit (REFOCON<15>) makes the clock signal available
on the REFO pin. The RODIV bits (REFOCON<11:8>)
enable the selection of 16 different clock divider
options.
The ROSSLP and ROSEL bits (REFOCON<13:12>)
control the availability of the reference output during
Sleep mode. The ROSEL bit determines if the oscillator
on OSC1 and OSC2, or the current system clock
source, is used for the reference clock output. The
ROSSLP bit determines if the reference source is
available on REFO when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for one of the primary
modes (EC, HS or XT); otherwise, if the ROSEL bit is
not also set, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
Reference Clock Output
(Register
family
2011 Microchip Technology Inc.
devices
9-4). Setting the ROEN
OSC
/2) available in
can
also
be
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