CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 97

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
The following is the sequence of operation for a single mixed-width Search command (also refer to Subsection 6.2, “Command
Bus Parameters,” on page 50).
Note. For 72-bit searches, the host ASIC must supply the same 72-bit data on DQ[71:0] during both cycles A and B. Also, the
even and odd pairs of GMRs selected for the comparison must be programmed with the same value. For 144-bit, 288-bit or 576-
bit searches, each 72-bit presented on each cycle A and B will together form the 144-bit or 288-bit or 576-bit search key
respectively.
When an N-bit search key, K, is presented on the DQ bus, the entire table of N-bit entries is compared to the search key using
the GMR and local mask bits. The GMR is selected by the GMR Index in the command’s cycle A. K is also stored in both even
and odd comparand register pairs (selected by the comparand register index in command cycle B). K is compared with each entry
in the table, starting at location 0. A matching entry that satisfies the Soft Priority and Mini-Key scheme (for Enhanced Mode) will
be the winning entry, and its location address L will be driven as part of the SRAM address on the SADR[N:0] lines (see
Section 6.7, “SRAM PIO Access,” on page 113), N = 25 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A. Note.
The Learn command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more
than one block.
For up to 31 devices in the table (TLSZ = 10 (binary)), Search latency is 6 from command to SRAM access cycle. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 6-8.
6.5.7
The multiple search operates the search commands in parallel on the upper half (array 0) and lower half (array 1) of the data
array in the device. The results from the two parallel searches are then driven on the SRAM bus at twice that rate relative to
single-search. The hardware diagram of the Search subsystem of up to eight devices is shown in Figure 6-43 below.
Note:
• Cycle A:
• Cycle B:
• MultiSearch feature is only available in the Enhanced Mode, not in the Non-Enhanced Mode.
• When MultiSearch is enabled, the maximum number of devices that can be cascaded is 8 if CLK2x is less than or equal to
• Comparing the hardware diagrams shown in Figure 6-10 and Figure 6-43, enabling MultiSearch does not mean that a board
• All eight devices must be programmed with the same values for TLZ (“01” (binary)) and HLAT (“000” (binary) in this example).
• The device receiving all the LHO signals from the other devices is considered the last device.
• All the shared signals in the following timing diagrams showing tri-stated condition (“z”) indicate that, that particular device is
• Comparing the hardware diagrams shown in Figure 6-10 and Figure 6-43, enabling MultiSearch does not mean that a board
200 MHz. The number of devices will be 4 if CLK2x operates above 200 MHz but up to 266 MHz.
layout change is required. The LHO_1_L and LHI_1_L share the same pin with the Full In and Full Out signals, which are not
shown in Figure 6-10. Cascading multiple devices together still allow the user to configure the devices through software to
perform single-search or MultiSearch operations without any board change.
Only the last device in the table must be programmed with LRAM = 1 (binary) and LDEV = 1 (binary) (device 7 in this case).
All other upstream devices must be programmed with LRAM = 0 (binary) and LDEV = 0 (binary) (devices 0 through 6 in this case).
not driving the shared signals. The shared signals are not three-stated in a real life because other devices will be driving them.
layout change is required. The LHO_1_L and LHI_1_L share the same pin with the Full In and Full Out signals, which are not
shown in Figure 6-10. Cascading multiple devices together still allow the user to configure the devices through software to
perform single-search or MultiSearch operations without any board change.
— Command Bus: The host ASIC drives CMDV HIGH and applies Search command CMD[1:0] = “10” (binary). The CMD[2]
— DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with the 72-bit data to be compared.
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10” (binary).
— DQ Bus: The DQ[71:0] continues to carry the search key to be compared.
and CMD[9] signals must be driven to logic 0 for the 72-bit search, but for 144-bit search, CMD[9] = 1 and CMD [2] = 0.
For 288-bit search, CMD[9] is don’t care, whereas CMD[2] = 1 for the first “A” cycle and 0 for the last “A” cycle.
{CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6]
signals must be driven with the same bits that will be driven on SADR[25:23] for CYNSE10512A, SADR[24:22] for
CYNSE10256A, SADR[23:21] for CYNSE10128A by this device if it has a hit. If Enhanced Mode and MultiSearch Enable
bits are both set to 1in the Command Resister, CMD[8] has to be set to 0 for Single Searches. For 288-bit and 576-bit Single
Searches, all Cycle A CMD[8] bits have to be set to 0’s.
CMD[5:2] must now be driven by the index of the comparand register pair for storing the search key presented on the DQ
bus during cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the
address of the matching entry and hit flag (see page 27 for a description of SSR[0:7]). CMD[10:9] are don’t cares for this cycle.
Mixed-size Multi Searches with 8 Devices on Tables Configured with Different Widths
CONFIDENTIAL
CYNSE10512A
CYNSE10256A
CYNSE10128A
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