CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 145

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
Document History Page
Document Title: CYNSE10512A/CYNSE10256A/CYNSE10128A Ayama 10000A Network Search Engine
Document Number: 38-02110
REV.
*A
*B
393322 See ECN
421311 See ECN
ECN
NO.
Issue
Date
Orig. of
Change
KMQ
CNG
VSP/
TNT
(continued)
Included PARERR_L into signal groupings with DQ in Figures 10-1 and 10-2.
Changed Figure 6-29 on page 83 to reflect 576 bits from bits 0 to 575 instead of 0 to 576.
Removed reference to blank “Figure” in section 6.3.3 Read Parity and replaced with
paragraph to explain read parity.
Added fact of internal pull-up of approximately 5 kohms to JTAG pins in section 7.0 on
page 125.
Changed ball AE1 in Figure 11-1 from VSS to HIGH_SPEEDI_L on page 135.
Changed REGSEL in Figure 5-31 to RSEL to remain consistent with Table 5-30
Changed description of Cycle 1 in sections 6.3.2 (Page 53) and 6.4.2 (Page 55), stating
that the addresses is provided in the RBURREG and WBURREG register, respectively.
Modified Figure 6-2 and Figure 6-4 to reflect address not supplied on DQ bus.
Changed Figure 6-5 on page 57 to illustrate HLAT = 000, rather than HLAT = 001.
Included “note” to page 26 regarding block number specification for block registers.
Changed “INDEX” field to “ADDRESS” field in RBURREG and WBURREG.
Created new Figure 6-5 explaining search key format on DQ bus.
Removed footnotes 31-35 as restrictions are no longer valid
Performed various sectional formatting, re-phrasing, and order changes for better ease of
flow
Corrected spelling and grammatical errors within document
Added description of GMR usage during Write commands in section 6.4
Added the respective power to all the signals from Page 12 -14.
Added description to the CFG_L pin in Page 12
Added Note 14 in Page 51 with explanation of the CMPR and SSR field in CMD[10:0]
Corrected the sentence to “Each of the four A-cycles provide a GMR index to mask 144
bits of the data to be compared (each A-cycle provide a pair of GMR, which is 144 bits,
four A-cycles will result in a total of 576 bits of GMR).” in Page 83.
Changed the title of Cascade interface to LVCMOS/HSTL I/II from LVCMOS/HSTL in Page
14
Added explanation for the behavior of the FULL signal during Write/Learn in Page 13 in
Signal description
Corrected Figure 5-12 so that it has the same DEVID width for various devices
Added Table 6-14 in Page 106 and also explanation for calculation of latency during a
learn command
Changed the GMR description in Page 27 to “When the device powers-up, the GMR
registers are initialized to 0. Figure 5-9 below shows each portion (Even, Odd) of each
GMR, and what address (in Decimal) is required to access that register.”
Corrected the EADR field in Page 50.This has been changed to SADR[25:23] for
CYNSE10512A, SADR[24:22] for CYNSE10256A, and SADR[23:20] for CYNSE10128A
from SADR[17:15],SADR[16:14],SADR[15:13] respectively
Removed the sentence “Learn operations with the address taken from the DQ bus... DQ
bus contains the address instead of Don't Cares” in Page 104
Changed the Note in Page 21 to focus the discussion on x144 and x288 searches.
Added small description of HLAT field behavior in associative data mode
Added a small note for the CPR multi-width field which is a don’t care for a single search
in Page 35
Corrected the description of SRR field in Page 36. There was a mention of SSR in the
description which was a typo
Figure 6-6: Changed the HLAT and TLSZ values to 001 and 01 respectively in Page 58
Figure 6-8: Changed TLSZ to be 01 in Page 60
Figure 6-49: Changed the TLSZ value to 01 and added one other SADR address A2 in
cycle 9 and corrected the OE_L, CE_L, ALE_L, values in Page 106
Figure 6-50: Changed the figure to suit the TLSZ value and the added changes to the
CE_L, ALE_L, WE_L and OLE_L signals. Added other address A2 for the CMPR register
in Page 107.
Figure 6-63: Changed the TLSZ value to 00 instead of 01 in Page 119
CONFIDENTIAL
Description of Change
CYNSE10512A
CYNSE10256A
CYNSE10128A
Page 145 of 145