CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 12

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
3.0
Table 3-1 lists and describes all Ayama 10000A signals.
Table 3-1. Ayama™ 10000A Signal Description
Clocks and Reset
CLK_MODE
CLK2X/CLK1X
PHS_L
RST_L
Configuration
CFG_L
ID[4:0]
ASICSEL
SRAMSEL
HSVREF0
HSVREF1
PARERR_L
ASIC Interface / Command and Data Buses (LVCMOS or HSTL I/II)
CMD[10:0]
CMDV
Notes:
1.
2.
I = Input only, I/O = input or output, O = output only (Always driven to 0 or 1, except when JTAG is enabled), OD = open-drain, T = three-state output.
The rise time of PARERR_L will depend on the value of the pull-up resistance. Sufficient delay should be allotted for in the error routine after clearing the parity
error in the parity control register and before this pin is sampled as part of the next command. Recommended external pull-up resistance range: 4.7K
Parameter
Signal Description
[2]
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ_SRAM
Type
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
Supply
O
I,
I,
I,
I,
I,
I,
I,
I,
I,
I,
I,
I,
[1]
,
Clock Mode. Selects the clock source for the device. When set to Low, the device uses both
CLK2X and PHS_L for its clock sources. When pulled High (V
CLK1X for its clock source (PHS_L must be externally grounded).
Master Clock. CLK_MODE selects either the CLK2X or CLK1X as the clock input signal.
CLK1X.
Input signals are sampled on both rising and falling edges. Output signals can be driven on
both falling and rising depending on the operation and the device configuration.
CLK2X
Input signals are sampled on the rising edge.Output signals are driven on the rising edge.
Phase. An input signal that must switch at half the frequency of CLK2X. This signal should
be pulled LOW when the device is in CLK1X mode. See Section 5.6, “Clocks,” on page 42.
Reset. Driving RST_L LOW initializes the device to the default state. The device becomes
active stable 4 CLK1X (8 CLK2X) cycles after RST_L is driven High (90% threshold).
Configuration. CFG_L is provided for backward compatibility with the older generation of
Cypress NSE CYNSE70000 devices, which had DQ bus width of 68-bits.When CFG_L is
set to Low, the device will tristate DQ[71:68]. If the Ayama 10000A is being operated as 72-
bit NSE, then CFG_L must be tied high to V
Device Identification. The binary-encoded device identification for a depth-cascaded
system starts at “00000” and goes up to “11110”. “11111” is reserved as the broadcast address
which selects all NSEs in the cascade.
On a broadcast Read, only the device with the LDEV bit set to ‘1’ will respond.
Any ID bit that is to be set High must be connected to V
ASIC IO Select. When this signal is pulled High (1.8V or 2.5V LVCMOS), the Command,
Data and Cascade buses will operate in LVCMOS mode. When tied to Low, the buses will
operate in HSTL mode.Signals affected by ASICSEL selection:
Clocks: CLK2X/CLK1X, PHS_L, RST_L
Command and Data:CMD[10:0], CMDV, DQ[71:0], PAR[1:0], ACK, EOT, SSF, SSV,
MULTI_HIT
Cascade Interface: LHI[6:0], LHO[1:0], BHI[2:0], BHO[2:0], FULI[6:0], FULO[1:0], FULL
SRAM IO Select. When this signal is pulled High (1.8V or 2.5V LVCMOS), the SRAM
Interface will operate in LVCMOS mode. When tied to Low, the interface will operate in HSTL
mode.Signals affected by SRAMSEL selection:SADR[25:0], CE_L, WE_L, OE_L, ALE_L
HSTL Reference Voltage. When ASICSEL is set to GND, this signal must be connected to
the HSTL reference voltage (VDDQ_ASIC/2). Otherwise, they should be left floating.
HSTL Reference Voltage. Refer to HSVREF0 description.
Parity Error. This signal is updated when there is a Core parity error or DQ Bus parity error.
It is an Active-Low Open-Drain signal that requires an external pull-up resistor to
VDDQ_ASIC. This signal is valid only after the device is fully initialized.
Command Bus. Bit[10:2] contains the command parameters and Bit[1:0] specifies the
command.
Command Valid. This signal indicates valid command in the CMD bus when set to High.
CONFIDENTIAL
Description
DDQ_ASIC
DDQ_ASIC
DDQ_ASIC
CYNSE10512A
CYNSE10256A
CYNSE10128A
.
), the device uses
Page 12 of 145
Ω
to 47K
Ω
.